Figure 8-5 illustrates a board layout example for the ADS981x. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference signals away from noise sources.

Use 0.1-μF ceramic bypass capacitors in close proximity to the AVDD_5V, VDD_1V8, and IOVDD power-supply pins. Avoid placing vias between the power-supply pins and the bypass capacitors.

Place the reference decoupling capacitor close to the device REFIO and REFM pins. Avoid placing vias between the REFIO pin and the bypass capacitors. Connect the GND, REFM, and IOGND pins to a ground plane using short, low-impedance paths.