ZHCSM18A January   2023  – December 2023 ADS9815 , ADS9817

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
        4. 6.3.1.4 Gain Error Calibration
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Reference
        1. 6.3.4.1 Internal Reference Voltage
        2. 6.3.4.2 External Reference Voltage
      5. 6.3.5 Sample Synchronization
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Test Patterns for Data Interface
          1. 6.3.6.3.1 User-Defined Test Pattern
          2. 6.3.6.3.2 User-Defined Alternating Test Pattern
          3. 6.3.6.3.3 Ramp Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down
      2. 6.4.2 Reset
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) System
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 CMOS Data Interface
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4.3 Initialization Sequence

As shown in Table 6-9, the ADS981x must be initialized by a sequence of register writes after device power-up or reset. A free-running sampling clock must be connected to the ADC before executing the initialization sequence. The ADS981x registers are initialized with the default value after the initialization sequence is complete.

Table 6-9 ADS981x Initialization Sequence
STEP NUMBER REGISTER COMMENT
BANK ADDRESS VALUE[15:0]
1 0 0x03 0x0002 Select register bank 1
2 1 0xF6 0x0002 INIT_2 = 1
3 0 0x04 0x000B INIT_1 = 1011b
4 0 0x03 0x0010 Select register bank 2
5 2 0x12 0x0040 INIT_3 = 1
6 2 0x13 0x8000 INIT_4 = 1
7 2 0x0A 0x4000 INIT_5 = 1
8 Wait 10 μs (min)
9 2 0x0A 0x0000 INIT_5 = 0
10 0 0x03 0x0002 Select register bank 1
11 1 0xF6 0x0000 INIT_2 = 0
12 0 0x03 0x0010 Select register bank 2
13 2 0x13 0x0000 INIT_5 = 0
14 2 0x12 0x0000 INIT_4 = 0
15 0 0x04 0x0000 INIT_1 = 0
16 0 0x03 0x0002 Select register bank 1
17 1 0x33 0x0030 Write INIT_KEY
18 1 0xF4 0x0000 INIT = 0
19 1 0xF4 0x0002 INIT = 1
20 Wait 1 ms (min)
21 1 0xF4 0x0000 INIT = 0
22 Wait 1 ms (min)
23 1 0x33 0x0000 INIT_KEY = 0
24 1 0x0D <user-defined> Enable gain error calibration and select ADC output data format
25 1 0x33 0x2040 Enable gain error calibration
26 1 0x34 0x0010 Enable gain error calibration

As shown in Table 6-10, the default settings of the ADS981x can be changed for user-defined configuration:

  • Analog inputs: analog input range, bandwidth, and common-mode voltage range
  • Data interface: number of output lanes, single or double data rate
Table 6-10 ADS981x User-Configuration
STEP REGISTER COMMENT
BANK ADDRESS VALUE[15:0]
1 1 0xC1 <user-defined> Configure data interface (data rate, number of lanes) and select internal or external reference
2 1 0xC2 and 0xC3 <user-defined> Select analog input ranges. See Table 6-1
3 1 0xC0 <user-defined> Select analog input bandwidth. See Table 6-2
4 1 0xC4 and 0xC5 <user-defined> Select common-mode range for analog inputs. See Table 6-3 and Table 6-4
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |