The SPI_READ register bit must be first set to 0 before writing to a register. When SPISTE is low:

• Serially shifting bits into the device is enabled.
• Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
• The serial data are loaded into the register at every 32nd SCLK rising edge.

In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and the remaining 24 bits form the register data. Figure 8-34 shows an SPI timing diagram for a single write operation. For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.

Figure 8-34 AFE SPI Write Timing Diagram