The device includes functionality where multiple read and write operations can be performed during a single SPISTE event. To enable this functionality, the first eight bits determine the register address to be written and the remaining 24 bits determine the register data. Perform two writes with the SPI read bit enabled during the second write operation in order to prepare for the read operation, as described in the Writing Data section. In the next command, specify the SPI register address with the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin. This functionality is described in the Writing Data and Reading Data sections. Figure 8-36 shows a timing diagram for the SPI multiple read and write operations.

The SPI read register bit must be enabled before attempting a serial readout from the AFE.

The second write operation must be configured for register 0 with data 000001h.

Specify the register address whose contents must be read back on A[7:0].

The AFE outputs the contents of the specified register on the SPISOMI pin.

Figure 8-36 Serial Multiple Read and Write Operations