ZHCSCL7C May 2014 – April 2021 AFE4403
PRODUCTION DATA
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
tCLK | Clock frequency on the XIN pin | 8 | MHz | ||
tSCLK | Serial shift clock period | 62.5 | ns | ||
tSTECLK | STE low to SCLK rising edge, setup time | 10 | ns | ||
tCLKSTEH,L | SCLK transition to SPI STE high or low | 10 | ns | ||
tSIMOSU | SIMO data to SCLK rising edge, setup time | 10 | ns | ||
tSIMOHD | Valid SIMO data after SCLK rising edge, hold time | 10 | ns | ||
tSOMIPD | SCLK falling edge to valid SOMI, setup time | 17 | ns | ||
tSOMIHD | SCLK rising edge to invalid data, hold time | 0.5 | tSCLK |