In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At each rising edge of the ADC reset signal, one averaged ADC conversion value is written into the output registers sequentially, as follows (see Figure 8-29):

• At the 25% reset signal, the first averaged ADC sample is written to register 2Ah (Decimal address = 42).
• At the 50% reset signal, the second averaged ADC sample is written to register 2Bh (Decimal address = 43).
• At the 75% reset signal, the third averaged ADC sample is written to register 2Ch (Decimal address = 44).
• At the next 0% reset signal, the fourth averaged ADC sample is written to register 2Dh (Decimal address = 45).
• Every time the registers 2Ah and 2Bh are updated, the contents of the difference register 2Eh is updated. Similarly, every time the registers 2Ch and 2Dh are updated, the contents of the difference register 2Fh is updated.

The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]). The user must specify the correct value for the number of averages, as described in Equation 6:

Equation 6.

Note that the 50-µs factor corresponds to a case where the internal clock of the AFE (after division) is exactly equal to 4 MHz. The factor scales linearly with the clock period being used.

Note that the number of average conversions is limited by 25% of the PRF. For example, eight samples can be averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz.

Figure 8-28 ADC Data Without Averaging (When Number of Averages = 0)

NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.

Figure 8-29 ADC Data with Averaging Enabled