SBASAC2 june 2023 AFE43902-Q1 , AFE53902-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: Voltage Output
- 6.6 Electrical Characteristics: ADC Input
- 6.7 Electrical Characteristics: General
- 6.8 Timing Requirements: I2C Standard Mode
- 6.9 Timing Requirements: I2C Fast Mode
- 6.10 Timing Requirements: I2C Fast Mode Plus
- 6.11 Timing Requirements: SPI Write Operation
- 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
- 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
- 6.14 Timing Requirements: PWM Output
- 6.15 Timing Diagrams
- 6.16 Typical Characteristics: Voltage Output
- 6.17 Typical Characteristics: ADC
- 6.18 Typical Characteristics: General
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 NOP Register (address = 00h) [reset = 0000h]
- 7.6.2 DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
- 7.6.3 COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
- 7.6.4 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
- 7.6.5 COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
- 7.6.6 GENERAL-STATUS Register (address = 22h) [reset = 2068h]
- 7.6.7 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
- 7.6.8 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
- 7.6.9 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
- 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
- 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
- 7.6.12 Xx-TEMPERATURE Register (SRAM address = 20h, 22h, 24h) [reset = 0000h]
- 7.6.13 Yx-TEMPERATURE Register (SRAM address = 21h, 23h, 25h) [reset = 0000h]
- 7.6.14 Xx-OUTPUT Register (SRAM address = 26h, 28h, 2Ah, 2Ch) [reset = 0000h]
- 7.6.15 Yx-OUTPUT Register (SRAM address = 27h, 29h, 2Bh, 2Dh) [reset = 0000h]
- 7.6.16 PWM-FREQUENCY Register (SRAM address = 2Eh) [reset = 0000h]
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
7.5.1 SPI Programming Mode
An SPI access cycle for the AFEx3902-Q1 is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be continuous or gated. SDI data are clocked on the SCLK falling edges. The SPI frame for the AFEx3902-Q1 is 24 bits long. Therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the SYNC pin is deasserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored. By default, the SDO pin is not enabled (three-wire SPI). In three-wire SPI mode, if the access cycle contains more than the minimum clock edges, only the first 24 bits are used by the device. When SYNC is high, the SCLK and SDI signals are blocked, and SDO becomes Hi-Z to allow data readback from other devices connected on the bus.
Table 7-6 and Figure 7-6 describe the format for the 24-bit SPI access cycle. The first byte input to SDI is the instruction cycle. The instruction cycle identifies the request as a read or write command and the 7-bit address that is to be accessed. The last 16 bits in the cycle form the data cycle.
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 23 | R/W | Identifies the communication as a read or write command to the address register: R/W = 0 sets a write operation. R/W = 1 sets a read operation |
| 22-16 | A[6:0] | Register address: specifies the register to be accessed during the read or write operation |
| 15-0 | DI[15:0] | Data cycle bits: If a write command, the data cycle bits are the values to be written to the register with address A[6:0]. If a read command, the data cycle bits are don't care values. |
Figure 7-6 SPI Write CycleRead operations require that the SDO pin is first enabled by setting the SDO-EN bit in the INTERFACE-CONFIG register. This configuration is called four-wire SPI. A read operation is initiated by issuing a read command access cycle. After the read command, a second access cycle must be issued to get the requested data. Table 7-7 and Figure 7-7 show the output data format. Data are clocked out on the SDO pin either on the falling edge or rising edge of SCLK according to the FSDO bit (see also Figure 6-3).
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 23 | R/W | Echo R/W from previous access cycle |
| 22-16 | A[6:0] | Echo register address from previous access cycle |
| 15-0 | DI[15:0] | Readback data requested on previous access cycle |
Figure 7-7 SPI Read CycleThe daisy-chain operation is also enabled with the SDO pin. Figure 7-8 shows that in daisy-chain mode, multiple devices are connected in a chain with the SDO pin of one device is connected to SDI pin of the following device. The SPI host drives the SDI pin of the first device in the chain. The SDO pin of the last device in the chain is connected to the POCI pin of the SPI host. In four-wire SPI mode, if the access cycle contains multiples of 24 clock edges, only the last 24 bits are used by the device first device in the chain. If the access cycle contains clock edges that are not in multiples of 24, the SPI packet is ignored by the device. Figure 7-9 describes the packet format for the daisy-chain write cycle.
Figure 7-8 SPI Daisy-Chain Connection
Figure 7-9 SPI Daisy-Chain Write Cycle