ZHCSGC8A March   2014  – June 2017 AFE5401-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Digital Characteristics
    7. 6.7  Timing Requirements: Output Interface
    8. 6.8  Timing Requirements: RESET
    9. 6.9  Timing Requirements: Serial Interface Operation
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Requirements: Across Output Serialization Modes
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Noise Amplifier (LNA)
      2. 8.3.2 Programmable Gain Amplifier (PGA)
      3. 8.3.3 Antialiasing Filter
      4. 8.3.4 Analog-to-Digital Converter (ADC)
      5. 8.3.5 Digital Gain
      6. 8.3.6 Input Clock Divider
      7. 8.3.7 Data Output Serialization
      8. 8.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 8.3.8.1 Main Channels
        2. 8.3.8.2 Auxiliary Channel
    4. 8.4 Device Functional Modes
      1. 8.4.1 Equalizer Mode
      2. 8.4.2 Data Output Mode
        1. 8.4.2.1 Header
        2. 8.4.2.2 Test Pattern Mode
      3. 8.4.3 Parity
      4. 8.4.4 Standby, Power-Down Mode
      5. 8.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 8.4.5.1 Decimate-by-2 Mode
        2. 8.4.5.2 Decimate-by-4 Mode
      6. 8.4.6 Diagnostic Mode
      7. 8.4.7 Signal Chain Probe
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
      2. 8.5.2 Register Initialization
        1. 8.5.2.1 Register Write Mode
        2. 8.5.2.2 Register Read Mode
      3. 8.5.3 CMOS Output Interface
        1. 8.5.3.1 Synchronization and Triggering
    6. 8.6 Register Maps
      1. 8.6.1 Functional Register Map
      2. 8.6.2 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage range DRVDD to DRVSS –0.3 +3.8 V
AVDD3 to AVSS –0.3 +3.8
AVDD18 to AVSS –0.3 +2.2
DVDD18 to DVSS –0.3 +2.2
Voltage between AVSS and DVSS –0.3 +0.3 V
AVSS and DRVSS –0.3 +0.3
DVSS and DRVSS –0.3 +0.3
Clock input pins (CLKINP and CLKINM) to AVSS –0.3 minimum (2.2, AVDD18 + 0.3) V
Analog input pins (INIP, INIM, INIP_AUX, and INIM_AUX) to AVSS –0.3 minimum (2.2, AVDD18 + 0.3) V
Digital control pins to DVSS STBY, RESET, SCLK, SDATA, SEN, TRIG –0.3 +3.6 V
Maximum operating junction temperature, TJ max +125 °C
Storage temperature, Tstg –60 +150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±1000 V
Charged-device model (CDM), per AEC Q100-011 ±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
TEMPERATURE
TA Ambient temperature range –40 +105 °C
SUPPLIES
DRVDD Output driver supply 1.7 3.6 V
AVDD3 3-V analog supply voltage 3 3.3 3.6 V
AVDD18 1.8-V analog supply voltage 1.7 1.8 1.9 V
DVDD18 1.8-V digital supply voltage 1.7 1.8 1.9 V
CLOCK INPUT
CLKIN Input clock frequency Default mode (DIV_EN disabled) 12.5 25 MHz
With DIV_EN, DIV_FRC enabled and DIV_REG = 1 25 50
With DIV_EN, DIV_FRC enabled and DIV_REG = 2 37.5 75
With DIV_EN, DIV_FRC enabled and DIV_REG = 3 50 100
With decimate-by-2 or decimate-by-4 modes enabled (DIV_EN disabled)(1) 12.5 50
VCLKINP – VCLKINM Input clock amplitude differential Sine wave, ac-coupled 0.2 1.5 VPP
LVPECL, ac-coupled 0.2 1.6
LVDS, ac-coupled 0.2 0.7
Single-ended CMOS clock on CLKINP with CLKINM connected to AVSS 1.8 V
Input clock duty cycle 40% 60%
DIGITAL OUTPUT
CLOAD Tolerable external load capacitance from each output pin to DRVSS 5 pF
(1) In decimation mode, input clock frequency (CLKIN) can be scaled up to maximum of 200 MHz with the input divider.

6.4 Thermal Information

THERMAL METRIC(1) AFE5401-Q1 UNIT
RGC (VQFN)
64 PINS
RθJA Junction-to-ambient thermal resistance 24.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 8.7 °C/W
RθJB Junction-to-board thermal resistance 3.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 3.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted. Typical values are at TNOM = +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FULL-CHANNEL CHARACTERISTICS
Maximum differential input signal amplitude on INIP and INIM LNA gain = 12 dB 0.5 VPP
LNA gain = 15 dB (default) 0.35
LNA gain = 16.5 dB 0.3
LNA gain = 18 dB 0.25
Input resistance, from each input to internal dc bias level Default 1 ± 20% kΩ
TERM_INT_20K_LNA / TERM_INT_20K_AUX = 1 10 ± 20%
CI Input capacitance Differential input capacitance 5.5 pF
VVCM VCM output voltage Voltage on VCM pins 1.45 V
VCM output current capability For 50-mV drop in VCM voltage 3 mA
Gain matching Across channels and devices 0.15 1 dB
EG Gain error PGA gain = 30 dB ± 0.6 ± 1.4 dB
EO Offset error PGA gain = 30 dB, 1 sigma value ± 120 LSB
Input-referred noise voltage fIN = 3 MHz, idle channel, PGA gain = 30 dB (default) 2.9 3.8 nV/√Hz
fIN = 3 MHz, idle channel, PGA gain = 30 dB
(HIGH_POW_LNA mode)		 2.5
SNR Signal-to-noise ratio fIN = 3 MHz, main channel 65 67.7 dBFS
fIN = 3 MHz, AUX channel 69.2
SFDR Spurious-free dynamic range fIN = 3 MHz, main channel (default) 57 66 dBc
fIN = 3 MHz, main channel (HPL_EN mode) 74
THD Total harmonic distortion fIN = 3 MHz, main channel 56 65 dBc
IMD Intermodulation distortion fIN1 = 1.5 MHz, fIN2 = 2 MHz, AIN1 and AIN2 = –7 dBFS 83 dBFS
PSRR Power-supply rejection ratio For a 50-mVPP signal on AVDD18 up to 10 MHz, no input applied to analog inputs > 50 dB
Number of bits in the ADC 12 Bits
Crosstalk, main channel to main channel Aggressor channel: fIN = 2 MHz, 1 dB below ADC full-scale.
Victim channel: fIN= 3 MHz, 1 dB below ADC full-scale.		 70 dB
Maximum channel gain LNA gain = 18 dB, PGA gain = 30 dB 48 dB
Minimum channel gain LNA gain = 12 dB, PGA gain = 0 dB 12 dB
PGA gain resolution 3 dB
PGA gain range Maximum PGA gain – minimum PGA gain 30 dB
Differential input voltage range for AUX channel 2 VPP
ANTIALIAS FILTER (Third-Order Elliptic)
fC 3-dB filter corner frequency FILTER_BW = 0 (default) 8 MHz
FILTER_BW = 1 7
FILTER_BW = 2 10.5
FILTER_BW = 3 12
3-dB filter corner frequency tolerance For all FILTER_BW settings ±5%
ATT2FC Filter attenuation At 2 × fC 30 dBc
ATTSTPBND Stop-band attenuation (fIN > 2.25 × fC) 40
RPPSBND Ripple in pass band 1.5 dB
POWER
Total core power, per channel Idle channel, excluding DRVDD power 64 mW
IAVDD18 AVDD18 current consumption Default mode 131 145 mA
With HIGH_POW_LNA mode enabled 153
With HPL_EN mode enabled 135
IAVDD3 AVDD3 current consumption 1.5 3.5 mA
IDVDD18 DVDD18 current consumption 8 12 mA
IDRVDD DRVDD current consumption 5-pF load, toggle data test pattern mode DRVDD = 3.3 V 14 mA
DRVDD = 1.8 V 8.5
15-pF load, toggle data test pattern mode DRVDD = 3.3 V 36
DRVDD = 1.8 V 20
Power-down 5 mW
STBY power 15 mW

6.6 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted. Typical values are at TNOM = +25°C.
PARAMETER MIN TYP MAX UNIT
DIGITAL INPUTS (STBY, RESET, SCLK, CLKIN, SDATA, SEN, TRIG)(1)
VIH High-level input voltage 1.4 V
VIL Low-level input voltage 0.4 V
IIH High-level input current 10 µA
IIL Low-level input current 10 µA
CI Input capacitance 4 pF
VIL_CLKINP Input clock CMOS single-ended (VCLKINP), VCLKINM connected to AVSS 0.25 × AVDD18 V
VIH_CLKINP 0.75 × AVDD18 V
DIGITAL OUTPUTS
VOH High-level output voltage DRVDD – 0.2 DRVDD V
VOL Low-level output voltage 0 0.2 V
(1) The SEN pin has an internal 150-kΩ pull-up resistor. The STBY, RESET, SCLK, SDATA, and TRIG pins have an internal 150-kΩ pull-down resistor.

6.7 Timing Requirements: Output Interface

Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with 0.1 µF, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted. Typical values are at TNOM = +25°C.
MIN NOM MAX UNIT
tADLY Aperture delay between the rising edge of the input sampling clock and the actual time at which the sampling occurs 3 ns
Wake-up time Time to valid data after coming out of STANDBY mode 500 µs
Time to valid data after coming out of GLOBAL_PDN mode 2 ms
Time to valid data after stopping and restarting the input clock 500 µs
tLAT ADC latency (default, after reset) 10.5 tAFE_CLK cycles
tSU Data setup time Data valid(1) to 50% of DCLK rising edge, DRVDD = 3.3 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0 4.1 ns
Data valid(1) to 50% of DCLK rising edge, DRVDD =1.8 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 5 3.7 ns
tHO Data hold time 50% of DCLK rising edge to data becoming invalid(1), DRVDD = 3.3 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0 2.8 ns
50% of DCLK rising edge to data becoming invalid(1), DRVDD = 1.8 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 5 2.7 ns
tR, tF CMOS output data and clock rise and fall time DRVDD = 3.3 V, load = 5 pF, 10% to 90%, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0 1.2 ns
DRVDD = 1.8 V, load = 5 pF, 10% to 90%, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 5 1.1 ns
tOUT Delay from CLKIN rising edge to DCLK rising edge, zero-crossing of input clock to 50% of DCLK rising edge, DRVDD = 3.3 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0 6.7 9.5 ns
tS_TRIG TRIG setup time, TRIG pulse duration ≥ tAFE_CLK 4 ns
tH_TRIG TRIG hold time, TRIG pulse duration ≥ tAFE_CLK 3 ns
(1) Data valid refers to a logic high of 0.7 × DRVDD and a logic low of 0.3 × DRVDD.

6.8 Timing Requirements: RESET

Typical values are at TA = +25°C. Minimum and maximum specifications are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 Power-on to reset delay Delay from power-up of AVDD18 and DVDD18 to RESET pulse active 1 ms
t2 Reset pulse duration Pulse duration of active RESET signal 40 ns
t3 Register write delay Delay from RESET disable to SEN active 100 ns

6.9 Timing Requirements: Serial Interface Operation

Minimum specifications are across the full temperature range of TMIN = –40°C to TMAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, CLOAD on SDOUT = 5 pF, unless otherwise noted.
PARAMETER MIN TYP MAX UNIT
t1 SCLK period 50 ns
t2 SCLK high time 20 ns
t3 SCLK low time 20 ns
t4 Data setup time 5 ns
t5 Data hold time 5 ns
t6 SEN falling to SCLK rising 8 ns
t7 Time between last SCLK rising edge to SEN rising edge 8 ns
t8 Delay from SCLK falling edge to SDOUT valid 7 11 15 ns
AFE5401-Q1 Systm_tmg_dgrm2_bas619.gif
1.

NOINDENT:

tCLK = 1 / fCLKIN
Figure 1. Output Interface Timing Diagram

A high pulse on the RESET pin is required for register initialization through the reset pin. Figure 2 shows the timing requirement for reset after power-up.

AFE5401-Q1 Rest_Tmg_bas619.gif Figure 2. Reset Timing
AFE5401-Q1 Srl_Intrfc_Rgstr_Wrt_bas619.gif Figure 3. Serial Interface Register Write Timing Diagram
AFE5401-Q1 Srl_Intrfc_Rgstr_Rd_bas619.gif Figure 4. Serial Interface Register Readout Timing Diagram

6.10 Typical Characteristics

Typical values are at TA = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.
AFE5401-Q1 C001_BAS619.png
SNR = 67.7 dBFS SFDR = 65.7 dBc THD = 65.2 dBc
Figure 5. FFT for 3-MHz, –1-dBFS Input Signal,
0-dB PGA Gain (Sample Rate = 25 MSPS)
AFE5401-Q1 C004_BAS619.png
fIN1 = 1.5 MHz Each Tone at –7-dBFS Amplitude
fIN2 = 2 MHz Two-Tone IMD = –83 dBFS
Figure 7. FFT with Two-Tone Signal
AFE5401-Q1 C005_BAS619.png
Figure 9. Signal-to-Noise Ratio vs Input Signal Frequency (PGA Gain = 0 dB)
AFE5401-Q1 C007_BAS619.png
Figure 11. Signal-to-Noise Ratio vs PGA Gain
AFE5401-Q1 C009_BAS619.png
Figure 13. Signal-to-Noise Ratio,
Spurious-Free Dynamic Range vs
Input Signal Amplitude (PGA Gain = 0 dB)
AFE5401-Q1 C011_BAS619.png
Figure 15. Signal-to-Noise Ratio vs Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-Q1 C013_BAS619.png
Figure 17. Signal-to-Noise Ratio vs Input Clock Duty Cycle (PGA Gain = 0 dB)
AFE5401-Q1 C045_BAS619.png
Figure 19. Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 0 dB)
AFE5401-Q1 C047_BAS619.png
Figure 21. Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 0 dB)
AFE5401-Q1 C015_BAS619.png
Figure 23. Signal-to-Noise Ratio vs AVDD18 and Temperature (PGA Gain = 0 dB)
AFE5401-Q1 C017_BAS619.png
Figure 25. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 0 dB, Default Mode)
AFE5401-Q1 C051_BAS619.png
Figure 27. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 0 dB, HPL_EN = 1)
AFE5401-Q1 C019_BAS619.png
Figure 29. Signal-to-Noise Ratio vs LNA Gain
(PGA Gain = 30 dB)
AFE5401-Q1 C021_BAS619.png
Figure 31. Input-Referred Noise vs LNA Gain
(PGA Gain = 30 dB)
AFE5401-Q1 C023_BAS619.png
Figure 33. Input-Referred Noise vs
PGA Gain and Temperature
AFE5401-Q1 C025_BAS619.png
Figure 35. Output-Referred Noise vs
PGA Gain and Temperature
AFE5401-Q1 C057_BAS619.png
Figure 37. Gain Matching Histogram (Maximum Gain Difference Among the Four Channels within a Device)
AFE5401-Q1 C058_BAS619.png
Figure 39. Offset Error Histogram at PGA Gain = 30 dB
AFE5401-Q1 C029_BAS619.png
Figure 41. Antialias Filter Response vs
FILTER_BW Settings (PGA Gain = 30 dB)
AFE5401-Q1 C053_BAS619.png
Figure 43. Antialias Filter Response vs Temperature (PGA Gain = 0 dB, FILTER_BW = 8 MHz)
AFE5401-Q1 C032_BAS619.png
Figure 45. Antialias Filter Response for Equalizer Modes (PGA Gain = 30 dB)
AFE5401-Q1 C036_BAS619.png
Figure 47. Antialias Filter Response for
Equalizer Modes across Temperature (PGA Gain = 30 dB)
AFE5401-Q1 C037_BAS619.png
Figure 49. Decimate-by-2 Filter Response (Sampling Frequency = 50 MHz)
AFE5401-Q1 C054_BAS619.png
Figure 51. Temperature Sensor Response
AFE5401-Q1 C040_BAS619.png
Figure 53. DVDD18 Supply Current vs Sampling Frequency
AFE5401-Q1 C042_BAS619.png
Figure 55. DRVDD Supply Current vs Sampling Frequency (15-pF Load with Toggle Test Mode)
AFE5401-Q1 C002_BAS619.png
SNR = 53.3 dBFS SFDR = 63.7 dBc THD = 63.6 dBc
Figure 6. FFT for 3-MHz, –1-dBFS Input Signal,
30-dB PGA Gain (Sample Rate = 25 MSPS)
AFE5401-Q1 C006_BAS619.png
Figure 8. Spurious-Free Dynamic Range vs
Input Signal Frequency
AFE5401-Q1 C050_BAS619.png
Figure 10. Signal-To-Noise Ratio vs Input Signal Frequency (PGA Gain = 30 dB)
AFE5401-Q1 C008_BAS619.png
Figure 12. Spurious-Free Dynamic Range vs PGA Gain
AFE5401-Q1 C010_BAS619.png
Figure 14. Signal-to-Noise Ratio,
Spurious-Free Dynamic Range vs
Input Signal Amplitude (PGA Gain = 30 dB)
AFE5401-Q1 C012_BAS619.png
Figure 16. Spurious-Free Dynamic Range vs
Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-Q1 C014_BAS619.png
Figure 18. Spurious-Free Dynamic Range vs
Input Clock Amplitude (PGA Gain = 0 dB)
AFE5401-Q1 C046_BAS619.png
Figure 20. Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 30 dB)
AFE5401-Q1 C048_BAS619.png
Figure 22. Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 30 dB)
AFE5401-Q1 C016_BAS619.png
Figure 24. Signal-to-Noise Ratio vs AVDD18 and Temperature (PGA Gain = 30 dB)
AFE5401-Q1 C018_BAS619.png
Figure 26. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 30 dB, Default Mode)
AFE5401-Q1 C052_BAS619.png
Figure 28. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 30 dB, HPL_EN = 1)
AFE5401-Q1 C020_BAS619.png
Figure 30. Spurious-Free Dynamic Range vs LNA Gain
(PGA Gain = 30 dB)
AFE5401-Q1 C022_BAS619.png
Figure 32. Input-Referred Noise vs PGA Gain
AFE5401-Q1 C024_BAS619.png
Figure 34. Output-Referred Noise vs PGA Gain
AFE5401-Q1 C056_BAS619.png
Figure 36. Gain Error Histogram for PGA Gain = 30 dB
AFE5401-Q1 C027_BAS619.png
Figure 38. Channel Offset vs
PGA Gain for Two Typical Devices
AFE5401-Q1 C028_BAS619.png
Figure 40. Antialias Filter Response vs
FILTER_BW Settings (PGA Gain = 0 dB)
AFE5401-Q1 C030_BAS619.png
Figure 42. Antialias Filter Response vs AVDD18
(PGA Gain = 0 dB, FILTER_BW = 8 MHz)
AFE5401-Q1 C031_BAS619.png
Figure 44. Antialias Filter Response for Equalizer Modes (PGA Gain = 0 dB)
AFE5401-Q1 C035_BAS619.png
Figure 46. Antialias Filter Response for
Equalizer Modes across Temperature (PGA Gain = 0 dB)
AFE5401-Q1 C049_BAS619.png
SNR = 69.2 dBFS SFDR = 69.8 dBc THD = 69.7 dBc
Figure 48. FFT for AUX Channel
(3-MHz, –1-dBFS Input Signal, Sample Rate = 25 MSPS)
AFE5401-Q1 C038_BAS619.png
Figure 50. Decimate-by-4 Filter Response (Sampling Frequency = 12.5 MHz)
AFE5401-Q1 C039_BAS619.png
Figure 52. AVDD18 Supply Current vs Sampling Frequency
AFE5401-Q1 C041_BAS619.png
Figure 54. AVDD3 Supply Current vs Sampling Frequency
AFE5401-Q1 C044_BAS619.png
Figure 56. AFE Core Power, Channel Excluding DRVDD
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |