米6体育平台手机版

ZHCSGC8A March 2014 – June 2017 AFE5401-Q1

PRODUCTION DATA.

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7 Parameter Measurement Information

7.1 Timing Requirements: Across Output Serialization Modes

Table 1 and Table 2 provide details for the 4x serialization timing requirements for DRVDD = 3.3 V and DRVDD = 1.8 V, respectively. Table 3 and Table 4 provide details for the 3x serialization timing requirements for DRVDD = 3.3 V and DRVDD = 1.8 V, respectively. Table 5 provides the details for the 2x and 1x serialization timing requirements for DRVDD = 1.8 V to 3.3 V.

Table 1. Timing Requirements: 4x Serialization (DRVDD = 3.3 V)

INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	SETUP TIME (ns) t_SU			HOLD TIME (ns) t_HO			t_OUT(ns)
INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
12.5	50	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	9.1			7.9			6.7		9.5
15	60	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	7.1			6.1			6.7		9.5
20	80	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	5.3			4.1			6.7		9.5
25	100	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	4.1			2.8			6.7		9.5
25	100	C_LOAD = 15 pF, STR_CTRL_CLK, STR_CTRL_DATA = 6	3.5			2.6			6.4		9.0

Table 2. Timing Requirements: 4x Serialization (DRVDD = 1.8 V)

INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	SETUP TIME (ns) t_SU			HOLD TIME (ns) t_HO			t_OUT(ns)
INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
12.5	50	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	9.2			7.9			5.6		10.6
15	60	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	7.2			6.1			5.6		10.6
20	80	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	5.3			3.9			5.6		10.6
25	100	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	3.7			2.7			5.6		10.6
25	100	C_LOAD = 15 pF, STR_CTRL_CLK and STR_CTRL_DATA = 14	2.6			2.7			5.3		10.0

Table 3. Timing Requirements: 3x Serialization (DRVDD = 3.3 V)

INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	SETUP TIME (ns) t_SU			HOLD TIME (ns) t_HO			t_OUT(ns)
INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
12.5	37.5	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	12.4			11.8			20.1		23.2
15	45	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	9.9			9.1			17.4		20.4
20	60	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	7.2			6.3			15.1		18.0
25	75	C_LOAD = 5 pF, STR_CTRL_CLK, STR_CTRL_DATA = 0	5.7			4.1			13.4		16.0
25	75	C_LOAD = 15 pF, STR_CTRL_CLK and STR_CTRL_DATA = 6	5.1			3.8			12.8		15.3

Table 4. Timing Requirements: 3x Serialization (DRVDD = 1.8 V)

INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	SETUP TIME (ns) t_SU			HOLD TIME (ns) t_HO			t_OUT(ns)
INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
12.5	37.5	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	12.5			11.9			19.2		23.6
15	45	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	10.0			9.3			16.6		20.1
20	60	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	7.3			6.4			14.0		18.4
25	75	C_LOAD = 5 pF, STR_CTRL_CLK and STR_CTRL_DATA = 5	5.7			4.7			12.4		16.7
25	75	C_LOAD = 15 pF, STR_CTRL_CLK and STR_CTRL_DATA = 14	4.7			4			12.1		16.4

Table 5. Timing Requirements: 2x and 1x Serialization (DRVDD = 1.8 V to 3.3 V)

INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	SETUP TIME (ns) t_SU			HOLD TIME (ns) t_HO			t_OUT(ns)
INPUT CLOCK FREQUENCY (MHz)	OUTPUT CLOCK (DCLK) FREQUENCY (MHz)	TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
25	50	2x Serialization mode: C_LOAD = 5 pF. For DRVDD = 1.8 V, STR_CTRL_CLK and STR_CTRL_DATA = 5. For DRVDD = 3.3 V, STR_CTRL_CLK and STR_CTRL_DATA = 0.	7.3			8.0			5.5		10.5
25	25	1x Serialization mode: C_LOAD = 5 pF. For DRVDD = 1.8 V, STR_CTRL_CLK and STR_CTRL_DATA = 5. For DRVDD = 3.3 V, STR_CTRL_CLK and STR_CTRL_DATA = 0.	18.5			17.5			25.2		30.1