11.1 Layout Guidelines

Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are particularly important for high-frequency designs. Achieving optimum performance with a high-performance device such as the AFE5809 requires careful attention to the PCB layout to minimize the effects of board parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows convenient component placement. To maintain proper LVDS timing, all LVDS traces should follow a controlled impedance design. In addition, all LVDS trace lengths should be equal and symmetrical; TI recommends to keep trace length variations less than 150 mil (0.150 inch or 3.81 mm).

In addition, appropriate delay matching should be considered for the CW clock path, especially in systems with high channel count. For example, if clock delay is half of the 16× clock period, a phase error of 22.5°C could exist. Thus, the timing delay difference among channels contributes to the beamformer accuracy.

Additional details on BGA PCB layout techniques can be found in the TI application report MicroStar BGA Packaging Reference Guide (SSYZ015), which can be downloaded from www.ti.com.

11.2 Layout Example

Figure 114. Layout Example

Figure 115. Layout Example

Figure 116. Layout Example

Figure 117. Layout Example