To maximize the performance of the AFEx8101 in any application, follow good layout
practices and proper circuit design. The following recommendations are specific to
the device:
- For best performance, dedicate an entire PCB layer to a
ground plane and do not route any other signal traces on this layer.
However, depending on restrictions imposed by specific end equipment, a
dedicated ground plane is not always practical. If ground-plane separation
is necessary, make a direct connection of the planes at the DAC. Do not
connect individual ground planes at multiple locations because this
configuration creates ground loops.
- IOVDD and PVDD must have 100-nF decoupling capacitors local
to the respective pins. VDD must have at least a 1-μF decoupling capacitor
used for the internal LDO, or for an
external 1.8-V supply. Use a high-quality ceramic-type NP0 or X7R
capacitor for best performance across temperature and a very low dissipation
factor.
- Place a 100-nF reference capacitor close to the VREFIO
pin.
- Avoid routing switching
signals near the reference input.
- Maintain proper placement for
the digital and analog sections with respect to the digital and analog
components. Separate the analog and digital circuitry for less coupling into
neighboring blocks and to minimize the interaction between analog and
digital return currents.
- For designs that include protection circuits:
- Place diversion
elements, such as TVS diodes or capacitors, close to off-board
connectors to make sure that return current from high-energy
transients does not cause damage to sensitive devices
- Use large, wide
traces to provide a low-impedance path to divert high-energy
transients away from the I/O pins.