ZHCSP80 December   2022 AFE78101 , AFE88101

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm Action Configuration Register
        2. 7.3.3.2 Alarm Voltage Generator
        3. 7.3.3.3 Temperature Sensor Alarm Function
        4. 7.3.3.4 Internal Reference Alarm Function
        5. 7.3.3.5 ADC Alarm Function
        6. 7.3.3.6 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 Internal Reference
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART
        1. 7.5.3.1 UART Break Mode (UBM)
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx8101 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

Figure 5-1 RRU (24-pin UQFN) Package, Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AIN0 15 AI ADC input voltage. The input range is 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V.
ALARM 24 DO Alarm notification. Open drain. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z).
CLK_OUT 11 DO Clock output. This pin can be configured as a clock output for the 1.2288‑MHz internal clock.
CS 10 DI SPI chip-select. Data bits are clocked into the serial shift register when CS is logic low. When CS is logic high, SDO is in a high-impedance state and data on SDI are ignored. Do not leave any digital input pins floating.
GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device.
GND 21, 22 P Digital and analog ground.
IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces.
NC 3, 23 – No connection. Leave floating.
POL_SEL/AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD > 2.7 V. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage.
PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input, and VOUT DAC output. When 2.7 V to 5.5 V is provided, the internal LDO turns on and drives VDD internally. When 1.71 V to 1.89 V is provided, the internal LDO is disabled.
REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin.
REF_GND 20 P GND reference for VREFIO pin.
RESET 6 DI Reset. Logic low on this pin places the device into power-down mode and resets the device. Logic high returns the device to normal operation. Do not leave any digital input pins floating.
SCLK 7 DI SPI serial clock. Data can be transferred at rates up to 12.5 MHz. SCLK is a Schmitt-trigger logic input. Connect to GND or logic low if not used. Do not leave any digital input pins floating.
SCLR 4 DI DAC clear input pin in SPI mode. A logic high on this pin forces the DAC output into a CLEAR state. Connect to GND in UBM. Do not leave any digital input pins floating.
SDI 8 DI SPI data input. Data are clocked into the 24‑bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-Trigger logic input. Do not leave any digital input pins floating.
SDO 9 DO SPI data output. Data are output on the rising edge of SCLK when CS is logic low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in a Hi-Z state at power up and must be enabled in the CONFIG register.
UARTIN 1 DI UART data input. Connect to IOVDD or logic high if not used. Do not leave any digital input pins floating.
UARTOUT 2 DO UART data output. This pin can be configured to function as the IRQ pin in SPI only mode.
VDD 13 P/AO Power supply. When 2.7 V to 5.5 V is provided on PVDD pin, the internal LDO drives VDD internally. Connect a 1‑μF to 10‑μF capacitor to this pin. When 1.71 V to 1.89 V is provided on the PVDD pin, an external power supply must be provided on this pin.
VOUT 18 AO DAC output voltage.
VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70-nF to 130-nF is required for stability. When disabled, this pin is the external 1.25‑V reference input.
(1) AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.
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