ZHCSP80 December 2022 AFE78101 , AFE88101
PRODUCTION DATA
The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points.
In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. Figure 7-9 shows the indexed custom channel sequence slots available in the device.
Table 7-5 lists the ADC input channel assignments for the sequencer.
| CCS POINTER | CHANNEL | CONV_RATE | RANGE |
|---|---|---|---|
| 0 | OFFSET | 2560 Hz | VREF |
| 1 | AIN0 | Programmable | Programmable |
| 2 | AIN1 | Programmable | Programmable |
| 3 | TEMP | 2560 Hz | VREF |
| 4 | SD0 (VREF) | 2560 Hz | VREF |
| 5 | SD1 (PVDD) | 2560 Hz | VREF |
| 6 | SD2 (VDD) | 2560 Hz | VREF |
| 7 | SD3 (ZTAT) | 2560 Hz | VREF |
| 8 | SD4 (VOUT) | 2560 Hz |
VREF when PVDD = 1.8 V 2 × VREF when PVDD ≥ 2.7 V |
| 9-15 | GND | 2560 Hz | VREF |
Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in Table 7-5. Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP.
In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared.
A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs.
Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. If PVDD ≥ 2.7 V, then the input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If PVDD = 1.8 V, then only the 0 V to 1.25 V range is allowed. In this case, the ADC_CFG.RANGE bit is prevented from being set.
If any ADC configuration bits are changed, the following sequence is recommended:
ADC_BUSY can be monitored in the GEN_STATUS register.
If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command.