ZHCSP80 December   2022 AFE78101 , AFE88101

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm Action Configuration Register
        2. 7.3.3.2 Alarm Voltage Generator
        3. 7.3.3.3 Temperature Sensor Alarm Function
        4. 7.3.3.4 Internal Reference Alarm Function
        5. 7.3.3.5 ADC Alarm Function
        6. 7.3.3.6 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 Internal Reference
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART
        1. 7.5.3.1 UART Break Mode (UBM)
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx8101 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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7.3.1 Digital-to-Analog Converter (DAC) Overview

The AFEx8101 feature a 16‑bit (AFE88101) or 14-bit (AFE78101) string DAC followed by an output voltage buffer. The DAC can be configured to support two low PVDD (0.15 V to 1.25 V and 0.2 V to 1 V), or high PVDD (0.3 V to 2.5 V and 0.4 V to 2 V) output ranges of operation depending on the PVDD supply voltage and the DAC_CFG.RANGE bit in the device configuration register. Using a voltage-to-current converter stage, these output voltages can be used to control a 4 mA to 20 mA loop. The narrow range corresponds to a 4-mA to 20-mA range. The full range allows for currents under and over the 4-mA to 20-mA range.

The devices continuously monitor the PVDD supply to provide proper operation based on the DAC range setting. Table 7-1 shows the valid supply ranges and corresponding VOUT DAC voltage ranges for the AFEx8101.

Table 7-1 VOUT DAC Voltage Ranges
DAC CONFIGURATION SUPPLY DAC_CFG.RANGE NAME VOUT DAC VOLTAGE RANGE
PVDD VDD
Invalid configuration 0 V ≤ PVDD < 1.71 V 0 V ≤ VDD < 1.71 V NA Alarm condition(1) 0.15 V or 1.25 V(2)
Low PVDD DAC range 1.71 V ≤ PVDD ≤ 1.89 V 1.71 V ≤ VDD ≤ 1.89 V 0 Full range 0.15 V to 1.25 V
1 Narrow range 0.2 V to 1 V
Invalid configuration 1.89 V < PVDD < 2.7 V VDD > 1.89 V NA Alarm condition(1) 0.15 V or 1.25 V(2)
High PVDD DAC range 2.7 V ≤ PVDD ≤ 5.5 V VDD is internally generated 0 Full range 0.3 V to 2.5 V
1 Narrow range 0.4 V to 2 V
Invalid configuration PVDD > 5.5 V VDD > 1.89 V NA Alarm condition(1) 0.3 V or 2.5 V(2)
(1) See Table 7-7 for details.
(2) See Figure 7-12 for details.

If PVDD or VDD fall outside the specified threshold values associated with the supply configuration during operation, an alarm is generated and the DAC output is set according to the ALARM_ACTION setting.
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