In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx81H1 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx81H1, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx81H1. See Figure 6-2 for UBM break character, communication timing details, and bit order.

Two baud rates are supported for UART communication: 9600 and 1200. The 9600 baud rate is default for UBM. The 1200 baud rate is supported to maintain backward compatibility and requires the use of SPI to communicate with the register map; whereas, the UART pins are used only for HART communication. The baud rates are selected by register bit CONFIG.UART_BAUD. When CONFIG.UART_BAUD = 1 (default), the UART operates at 9600 baud. When CONFIG.UART_BAUD = 0, the UART operates at 1200 baud. The break function of the UART protocol is enabled only for 9600 baud. This configuration allows interleaving of HART data with register communication and enables the access to all registers of the device, when configured correctly.

Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM.

A UBM data output packet is initiated by AFEx81H1 on UARTOUT in two cases. See Figure 7-33 for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. For details on HART data see Section 7.5.3.1.1.

To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx81H1 triggers a break command followed by data on UARTOUT (see Figure 7-33).

The contents of the data are listed in order of priority below.

1. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output.
2. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output.
3. If MODEM_IRQ bit is set, then the contents of the MODEM_STATUS register are output.
4. If none of the previous bits are set, then an IRQ is not generated.

A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see Figure 7-30). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first.

Figure 7-34 shows the data structure of the UBM write command, and Figure 7-32 shows the data structure of the UBM read command.

Figure 7-31 UARTIN Break Write Data Format

Figure 7-32 UARTIN Break Read Data Format

Figure 7-33 shows the UARTOUT data frame with details of the status bits produced by the AFEx81H1. See Table 7-12 for details.

Figure 7-33 UARTOUT Break Data Format