ZHCSOT2C january   2022  – may 2023 AFE7906

PRODUCTION DATA  

  1.   1
  2. 1特性
  3. 2应用
  4. 3说明
  5. 4说明（续）
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  RF ADC Electrical Characteristics
    6. 6.6  PLL/VCO/Clock Electrical Characteristics
    7. 6.7  Digital Electrical Characteristics
    8. 6.8  Power Supply Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
      1. 6.11.1 RX Typical Characteristics 30 MHz and 400 MHz
      2. 6.11.2 RX Typical Characteristics at 800MHz
      3. 6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 6.11.4 RX Typical Characteristics 2.6GHz
      5. 6.11.5 RX Typical Characteristics 3.5GHz
      6. 6.11.6 RX Typical Characteristics 4.9GHz
      7. 6.11.7 RX Typical Characteristics 6.8GHz
      8. 6.11.8 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 接收文档更新通知
    2. 7.2 支持资源
    3. 7.3 Trademarks
    4. 7.4 静电放电警告
    5. 7.5 术语表
  9. 8Mechanical, Packaging, and Orderable Information

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6.6 PLL/VCO/Clock Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; Reference clock input frequency 491.52MHz (unless otherwise noted), phase noise normalized to fVCO.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fVCO1 VCO1 min frequency 7.2 GHz
VCO1 max frequency 7.68 GHz
fVCO2 VCO2 min frequency 8.848 GHz
VCO2 max frequency 9.216 GHz
fVCO3 VCO3 min frequency 9.8304 GHz
VCO3 max frequency 10.24 GHz
fVCO4 VCO4 min frequency 11.7965 GHz
VCO4 max frequency 12.288 GHz
DIVFBADC ADC sample rate divider from VCO rate 1, 2, 3, 4, 6 or 8
DIVRXADC ADC sample rate divider 1, 2, 3, 4, 6 or 8
PNVCO Closed Loop Phase Noise FPLL = 11.79848 GHz FREF=491.52MHz 600kHz -113 dBc/Hz
800kHz -116 dBc/Hz
1MHz -119 dBc/Hz
1.8MHz -125 dBc/Hz
5MHz -133 dBc/Hz
50MHz –141 dBc/Hz
Closed Loop Phase Noise FPLL=8.84736 GHz FREF=491.52MHz 600kHz -114 dBc/Hz
800kHz –118 dBc/Hz
1MHz –120 dBc/Hz
1.8MHz –127 dBc/Hz
5MHz –135 dBc/Hz
50MHz –142 dBc/Hz
Closed Loop Phase Noise FPLL= 9.8403 GHz FREF=491.52MHz 600kHz –113 dBc/Hz
800kHz –116 dBc/Hz
1MHz –119 dBc/Hz
1.8MHz –125 dBc/Hz
5MHz –134 dBc/Hz
50MHz –140 dBc/Hz
Closed Loop Phase Noise FPLL= 7.86432GHz FREF=491.52MHz 600kHz –116 dBc/Hz
800kHz –119 dBc/Hz
1MHz –122 dBc/Hz
1.8MHz –127 dBc/Hz
5MHz –136 dBc/Hz
50MHz –143 dBc/Hz
Frms Clock PLL integrated phase error(1) fPLL=11.79848 GHz, [1KHz, 100MHz] -43.4 dBc/Hz
fPLL=8.8536 GHz, [1KHz, 100MHz] -47.6 dBc/Hz
fPLL=9.8304 GHz, [1KHz, 100MHz] -46.2 dBc/Hz
fPFD PFD frequency 100 500 MHz
PNpll_flat Normalized PLL flat Noise fVCO = 11796.48MHz –226.5 dBc/Hz
FREF Input Clock frequency 0.1 12 GHz
VSS Input Clock level 0.6 1.8 Vppdiff
Coupling AC Coupling Only
REFCLK input impedance(2) Parallel resistance 100 Ω
Parallel capacitance 0.5 pF
(1) Single Sideband, not including the reference clock contribution
(2) Refer to S11 data available from TI for impedance vs frequency
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