Typical values at T_A = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, f_DAC = 11796.48MSPS (24x interpolation), interleave mode, 1^st Nyquist zone output, PLL clock mode with f_REF = 491.52MHz, A_OUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated

including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 0.8GHz matching

Figure 4-1 TX Output Fullscale vs Output Frequency

fDAC = 11796.48MSPS, interleave mode, Aout = -0.5dFBS, matching 0.8GHz

Figure 4-3 TX Output Power vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-5 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting

Figure 4-7 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-9 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting

Figure 4-11 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Phase DNL spike may occur at any DSA setting.

Figure 4-13 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 4-15 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz, channel with the median variation over DSA setting at 25°C

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) + 1

Figure 4-17 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 4-19 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85GHz, matching at 0.8 GHz, –13 dBFS each tone

Figure 4-21 TX IMD3 vs DSA Setting at 0.85GHz

fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone

Figure 4-23 TX IMD3 vs Tone Spacing and Channel at 0.85GHz

fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone, worst channel

Figure 4-25 TX IMD3 vs Tone Spacing and Temperature at 0.85GHz

fDAC = 11796.48MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone, worst channel

Figure 4-27 TX IMD3 vs Tone Spacing and Temperature at 0.85GHz

fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85GHz, fSPACING = 20MHz, matching at 0.8GHz

Figure 4-29 TX IMD3 vs Digital Level at 0.85GHz

Matching at 2.6GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40MHz offset, DSA = 0dB

Figure 4-31 TX Single Tone Output Noise vs Frequency and Amplitude at 0.85GHz

Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-33 TX 20-MHz LTE ACPR vs Digital Level at 0.85GHz

Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-35 TX 20MHz LTE ACPR vs DSA at 0.85GHz

Matching at 0.8GHz, fDAC = 5898.2 GSPS, straight mode

Figure 4-37 TX HD2 vs Digital Amplitude and Output Frequency at 0.85GHz

Matching at 0.8GHz, fDAC = 5898.24MSPS, straight mode, normalized to output power at harmonic frequency

Figure 4-39 TX HD3 vs Digital Amplitude and Output Frequency at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, 0.8GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 4-41 TX Single Tone (–12 dBFS) Output Spectrum at 0.85GHz (0-f_DAC)

fDAC = 5898.24MSPS, interleave mode, 0.8GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 4-43 TX Single Tone (–1dBFS) Output Spectrum at 0.85GHz (0-f_DAC)

including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 0.8GHz matching

Figure 4-2 TX Output Fullscale vs Temperature

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-4 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Settings

Figure 4-6 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-8 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting

Figure 4-10 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 4-12 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 4-14 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) + 1

Figure 4-16 TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 4-18 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 0.85GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8GHz, POUT = –13 dBFS

Figure 4-20 TX Output Noise vs Channel and Attenuation at 0.85GHz

fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone

Figure 4-22 TX IMD3 vs Tone Spacing and Channel at 0.85GHz

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85GHz, matching at 0.8GHz, –13dBFS each tone

Figure 4-24 TX IMD3 vs Tone Spacing and Channel at 0.85GHz

DAC = 8847.3 MSPS, straight mode, fCENTER = 0.85GHz, matching at 0.8 GHz, –13dBFS each tone, worst channel

Figure 4-26 TX IMD3 vs Tone Spacing and Temperature at 0.85GHz

fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85GHz, fSPACING = 20MHz, matching at 0.8GHz

Figure 4-28 TX IMD3 vs Digital Level at 0.85GHz

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85GHz, fSPACING = 20MHz, matching at 0.8GHz

Figure 4-30 TX IMD3 vs Digital Level at 0.85GHz

TM1.1, POUT_RMS = –13dBFS

Figure 4-32 TX 20-MHz LTE Output Spectrum at 0.85 GHz

Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-34 TX 20MHz LTE alt-ACPR vs Digital Level at 0.85GHz

Matching at 0.8GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-36 TX 20-MHz LTE alt-ACPR vs DSA at 0.85GHz

Matching at 0.8GHz, fDAC = 8847.36GSPS, straight mode

Figure 4-38 TX HD2 vs Digital Amplitude and Output Frequency at 0.85GHz

Matching at 0.8GHz, fDAC = 8847.36MSPS, straight mode, normalized to output power at harmonic frequency

Figure 4-40 TX HD3 vs Digital Amplitude and Output Frequency at 0.85GHz

fDAC = 5898.2 MSPS, interleave mode, 0.8GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 4-42 TX Single Tone (–6dBFS) Output Spectrum at 0.85GHz (0-f_DAC)