Typical values at T_A = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, f_DAC = 11796.48MSPS (24x interpolation), interleave mode, 1^st Nyquist zone output, PLL clock mode with f_REF = 491.52MHz, A_OUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated

Excluding PCB and cable losses, Aout = -0.5 dFBS, DSA = 0, 4.9GHz matching

Figure 4-149 TX Full Scale vs RF Frequency and Channel at 11796.48MSPS

fDAC = 11796.48MSPS, Aout = -0.5dFBS, matching 4.9GHz

Figure 4-151 TX Output Power vs DSA Setting and Channel at 4.9GHz

fDAC =11796.48MSPS, interleave mode, matching at 4.9GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-153 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleave mode, matching at 4.9GHz

Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)

Figure 4-155 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-157 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)

Figure 4-159 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Phase DNL spike may occur at any DSA setting.

Figure 4-161 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 4-163 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 4-165 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, channel with the median variation over DSA setting at 25°C

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 4-167 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, fCENTER = 4.9GHz, -13 dBFS each tone

Figure 4-169 TX IMD3 vs DSA Setting at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, fCENTER = 4.9GHz, –13 dBFS each tone, worst channel

Figure 4-171 TX IMD3 vs Tone Spacing and Temperature at 4.9GHz

Matching at 4.9GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40MHz offset, DSA = 0dB

Figure 4-173 TX Single Tone Output Noise vs Frequency and Amplitude at 4.9GHz

Matching at 4.9GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-175 TX 20MHz LTE ACPR vs Digital Level at 4.9GHz

Matching at 4.9GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-177 TX 20MHz LTE ACPR vs DSA at 4.9GHz

Matching at 4.9GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency

Figure 4-179 TX HD2 vs Digital Amplitude and Output Frequency at 4.9GHz

fDAC = 11796.48MSPS, interleave mode, 4.9GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 4-181 TX Single Tone (–12 dBFS) Output Spectrum at 4.9GHz (0-f_DAC)

fDAC = 11796.48MSPS, interleave mode, 4.9GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 4-183 TX Single Tone (–1 dBFS) Output Spectrum at 4.9GHz (0-f_DAC)

Excluding PCB and cable losses, Aout = -0.5 dFBS, DSA = 0, 4.9GHz matching

Figure 4-150 TX Full Scale vs RF Frequency and Channel at 5898.24 MSPS, Straight Mode, 2nd Nyquist Zone

fDAC =11796.48MSPS, interleave mode, matching at 4.9GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-152 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 4.9GHz

fDAC =11796.48MSPS, interleave mode, matching at 4.9GHz

Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)

Figure 4-154 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-156 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)

Figure 4-158 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 4-160 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 4-162 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 4-164 TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 4-166 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, POUT = –13 dBFS

Figure 4-168 TX Output Noise vs Channel and Attenuation at 2.6GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, fCENTER = 4.9GHz, –13 dBFS each tone

Figure 4-170 TX IMD3 vs Tone Spacing and Channel at 4.9GHz

fDAC = 11796.48MSPS, interleaved mode, matching at 4.9GHz, fCENTER = 4.9GHz, fSPACING = 20MHz

Figure 4-172 TX IMD3 vs Digital Level at 4.9GHz

TM1.1, POUT_RMS = –13dBFS

Figure 4-174 TX 20MHz LTE Output Spectrum at 4.9GHz

Matching at 4.9GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-176 TX 20MHz LTE alt-ACPR vs Digital Level at 4.9GHz

Matching at 4.9GHz, single carrier 20MHz BW TM1.1 LTE

Figure 4-178 TX 20MHz LTE alt-ACPR vs DSA at 4.9GHz

Matching at 4.9GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency

Figure 4-180 TX HD3 vs Digital Amplitude and Output Frequency at 4.9GHz

fDAC = 11796.48MSPS, interleave mode, 4.9GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 4-182 TX Single Tone (–6 dBFS) Output Spectrum at 4.9GHz (0-f_DAC)