Typical values at T_A = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, f_DAC = 11796.48MSPS (24x interpolation), interleave mode, 1^st Nyquist zone output, PLL clock mode with f_REF = 491.52MHz, A_OUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated

Aout = -0.5dFBS, 3.5GHz Matching, included PCB and cable losses

Figure 4-118 TX Output Power vs Frequency

3.5GHz Matching, included PCB and cable losses

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-120 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)

Figure 4-122 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Figure 4-124 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Figure 4-126 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, 1TX

Figure 4-128 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 3.5GHz

3.5GHz Matching, 1TX

Figure 4-130 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz

3.5GHz Matching, 1TX

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 4-132 TX Uncalibrated Differential Phase Error vs DSA setting and Temperature at 3.5GHz

3.5GHz Matching, 1TX

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting=0)

Figure 4-134 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz

A.

fDAC =11796.48MSPS, interleave mode, matching at 3.5GHz, Aout = –13 dBFS.

Figure 4-136 TX NSD vs DSA Setting at 3.5GHz

20MHz tone spacing, 3.5GHz Matching

Figure 4-138 TX IMD3 vs Digital Amplitude and Channel at 3.5GHz

3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE

Figure 4-140 TX 20MHz LTE ACPR vs DSA Setting at 3.5GHz

3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE

Figure 4-142 TX 20MHz LTE ACPR vs Digital Level at 3.5GHz

Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency

Figure 4-144 TX Single Tone HD2 vs Frequency and Digital Level at 3.5GHz

Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode.

Figure 4-146 TX Single Tone (–1dBFS) Output Spectrum at 3.5GHz (0 - f_DAC)

Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode.

Figure 4-148 TX Single Tone (–12dBFS) Output Spectrum at 3.5GHz (0-f_DAC)

Aout = -0.5dFBS, 3.5GHz Matching, included PCB and cable losses

Figure 4-119 TX Output Power vs DSA Setting at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 4-121 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting)

Figure 4-123 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Phase DNL spike may occur at any DSA setting.

Figure 4-125 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, included PCB and cable losses

Figure 4-127 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 3.5GHz

3.5GHz Matching, 1TX, Calibrated at 25°C

Figure 4-129 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 3.5GHz

3.5GHz Matching, 1TX, Calibrated at 25°C

Figure 4-131 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5GHz

3.5GHz Matching, 1TX, Calibrated at 25°C

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 4-133 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 3.5GHz

3.5GHz Matching, 1TX, Calibrated at 25°C

Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)

Figure 4-135 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5GHz

20MHz tone spacing, 3.5GHz Matching, –13 dBFS each tone, included PCB and cable losses

Figure 4-137 TX IMD3 vs DSA Setting at 3.5GHz

3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE

Figure 4-139 TX 20MHz LTE Output Spectrum at 3.5GHz (Band 42)

3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE

Figure 4-141 TX 20MHz LTE alt-ACPR vs DSA Setting at 3.5GHz

3.5GHz Matching, single carrier 20MHz BW TM1.1 LTE

Figure 4-143 TX 20MHz LTE alt-ACPR vs Digital Level at 3.5GHz

Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode, normalized to output power at harmonic frequency. Dip is due to HD3 falling near DC.

Figure 4-145 TX Single Tone HD3 vs Frequency and Digital Level at 3.5GHz

Matching at 3.5GHz, fDAC = 11.79648GSPS, interleave mode.

Figure 4-147 TX Single Tone (–6dBFS) Output Spectrum at 3.5GHz (0-f_DAC)