米6体育平台手机版

ZHCSPA8A March 2024 – August 2024 AFE7950-SP

PRODMIX

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机械数据 (封装 | 引脚)

ALK|400
- MPBGAU3B

散热焊盘机械数据 (封装 | 引脚)

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4.7 PLL/VCO/Clock Electrical Characteristics

Typical values at TA = +25°C, full temperature range is T_A,MIN = -40°C to T_J,MAX = +110°C; Reference clock input frequency 491.52MHz (unless otherwise noted), f_DAC = f_VCO, f_OUT = f_DAC/4, normalized to f_VCO.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_VCO1	VCO1 min frequency				7.2	GHz
f_VCO1	VCO1 max frequency		7.68			GHz
f_VCO2	VCO2 min frequency				8.8	GHz
f_VCO2	VCO2 max frequency		9.1			GHz
f_VCO3	VCO3 min frequency				9.7	GHz
f_VCO3	VCO3 max frequency		10.24			GHz
f_VCO4	VCO4 min frequency				11.6	GHz
f_VCO4	VCO4 max frequency		12.08			GHz
DIV_DAC	DAC sample rate divider			1, 2 or 3
DIV_FBADC	ADC sample rate divider from DAC sample rate			1, 2, 3, 4, 6 or 8
DIV_RXADC	ADC sample rate divider			1, 2, 3, 4, 6 or 8
PN_VCO	Closed Loop Phase Noise F_PLL= 11.79848 GHz F_REF=491.52MHz	600kHz		-113		dBc/Hz
		800kHz		-116		dBc/Hz
		1MHz		-119		dBc/Hz
		1.8MHz		-125		dBc/Hz
		5MHz		-133		dBc/Hz
		50MHz		–141		dBc/Hz
	Closed Loop Phase Noise F_PLL=8.84736 GHz F_REF=491.52MHz	600kHz		-114		dBc/Hz
		800kHz		–118		dBc/Hz
		1MHz		–120		dBc/Hz
		1.8MHz		–127		dBc/Hz
		5MHz		–135		dBc/Hz
		50MHz		–142		dBc/Hz
	Closed Loop Phase Noise F_PLL= 9.8403 GHz F_REF=491.52MHz	600kHz		–113		dBc/Hz
		800kHz		–116		dBc/Hz
		1MHz		–119		dBc/Hz
		1.8MHz		–125		dBc/Hz
		5MHz		–134		dBc/Hz
		50MHz		–140		dBc/Hz
	Closed Loop Phase Noise F_PLL= 7.86432GHz F_REF=491.52MHz	600kHz		–116		dBc/Hz
		800kHz		–119		dBc/Hz
		1MHz		–122		dBc/Hz
		1.8MHz		–127		dBc/Hz
		5MHz		–136		dBc/Hz
		50MHz		–143		dBc/Hz
F_rms	Clock PLL integrated phase error⁽¹⁾	f_PLL=11.79848 GHz, [1KHz, 100MHz]		-43.4		dBc/Hz
		f_PLL=8.8536 GHz, [1KHz, 100MHz]		-47.6		dBc/Hz
		f_PLL=9.8304 GHz, [1KHz, 100MHz]		-46.2		dBc/Hz
f_PFD	PFD frequency		100		500	MHz
F_REF	Input clock minimum frequency			0.1		GHz
F_REF	Input Clock maximum frequency			12		GHz
V_CLKMIN	Input clock minimum level			0.6		Vppdiff
V_CLKMAX	Input Clock maximum level			1.8		Vppdiff
PN_{pll_flat}	Normalized PLL flat Noise	f_VCO = 11796.48MHz		–226.5		dBc/Hz
Coupling				AC Coupling Only
	REFCLK input impedance⁽²⁾	Parallel resistance		100		Ω
	REFCLK input impedance⁽²⁾	Parallel capacitance		0.5		pF

(1) Single Sideband, not including the reference clock contribution

(2) Refer to S11 data available from TI for impedance vs frequency