Typical values at T_A = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, f_DAC = 11796.48MSPS (24x interpolation), interleave mode, 1^st Nyquist zone output, PLL clock mode with f_REF = 491.52 MHz, A_OUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled

including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 0.8 GHz matching

Figure 6-1 TX Output Fullscale vs Output Frequency

fDAC = 11796.48 MSPS, interleave mode, Aout = -0.5dFBS, matching 0.8 GHz

Figure 6-3 TX Output Power vs DSA Setting and Channel at 0.85 GHz

fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 6-5 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 0.85 GHz

fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting

Figure 6-7 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 6-9 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting

Figure 6-11 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Phase DNL spike may occur at any DSA setting.

Figure 6-13 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 6-15 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz, channel with the median variation over DSA setting at 25°C

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) + 1

Figure 6-17 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 6-19 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone

Figure 6-21 TX IMD3 vs DSA Setting at 0.85 GHz

fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone

Figure 6-23 TX IMD3 vs Tone Spacing and Channel at 0.85 GHz

fDAC = 5898.24MSPS, straight mode, fCENTER =0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone, worst channel

Figure 6-25 TX IMD3 vs Tone Spacing and Temperature at 0.85 GHz

fDAC = 11796.48MSPS, straight mode, fCENTER =0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone, worst channel

Figure 6-27 TX IMD3 vs Tone Spacing and Temperature at 0.85 GHz

fDAC = 8847.36MSPS, straight mode, fCENTER = 0.85 GHz, fSPACING = 20 MHz, matching at 0.8 GHz

Figure 6-29 TX IMD3 vs Digital Level at 0.85 GHz

Matching at 2.6 GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40-MHz offset, DSA = 0dB

Figure 6-31 TX Single Tone Output Noise vs Frequency and Amplitude at 0.85 GHz

Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE

Figure 6-33 TX 20-MHz LTE ACPR vs Digital Level at 0.85 GHz

Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE

Figure 6-35 TX 20-MHz LTE ACPR vs DSA at 0.85 GHz

Matching at 0.8 GHz, fDAC = 5898.24GSPS, straight mode

Figure 6-37 TX HD2 vs Digital Amplitude and Output Frequency at 0.85 GHz

Matching at 0.8 GHz, fDAC = 5898.24MSPS, straight mode, normalized to output power at harmonic frequency

Figure 6-39 TX HD3 vs Digital Amplitude and Output Frequency at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, 0.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 6-41 TX Single Tone (–12 dBFS) Output Spectrum at 0.85 GHz (0-f_DAC)

fDAC = 5898.24MSPS, interleave mode, 0.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 6-43 TX Single Tone (–1 dBFS) Output Spectrum at 0.85 GHz (0-f_DAC)

including PCB and cable losses, Aout = -0.5dFBS, DSA = 0, 0.8 GHz matching

Figure 6-2 TX Output Fullscale vs Temperature

fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 6-4 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 0.85 GHz

fDAC=5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Settings

Figure 6-6 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1

Figure 6-8 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting

Figure 6-10 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting)

Figure 6-12 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 6-14 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) + 1

Figure 6-16 TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz

Integrated Phase Error = PhaseOUT(DSA Setting) – PhaseOUT(DSA Setting = 0)

Figure 6-18 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, matching at 0.8 GHz, POUT = –13 dBFS

Figure 6-20 TX Output Noise vs Channel and Attenuation at 0.85 GHz

fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone

Figure 6-22 TX IMD3 vs Tone Spacing and Channel at 0.85 GHz

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone

Figure 6-24 TX IMD3 vs Tone Spacing and Channel at 0.85 GHz

fDAC = 8847.36MSPS, straight mode, fCENTER =0.85 GHz, matching at 0.8 GHz, –13 dBFS each tone, worst channel

Figure 6-26 TX IMD3 vs Tone Spacing and Temperature at 0.85 GHz

fDAC = 5898.24MSPS, straight mode, fCENTER = 0.85 GHz, fSPACING = 20 MHz, matching at 0.8 GHz

Figure 6-28 TX IMD3 vs Digital Level at 0.85 GHz

fDAC = 11796.48MSPS, interleave mode, fCENTER = 0.85 GHz, fSPACING = 20 MHz, matching at 0.8 GHz

Figure 6-30 TX IMD3 vs Digital Level at 0.85 GHz

TM1.1, POUT_RMS = –13 dBFS

Figure 6-32 TX 20-MHz LTE Output Spectrum at 0.85 GHz

Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE

Figure 6-34 TX 20-MHz LTE alt-ACPR vs Digital Level at 0.85 GHz

Matching at 0.8 GHz, single carrier 20-MHz BW TM1.1 LTE

Figure 6-36 TX 20-MHz LTE alt-ACPR vs DSA at 0.85 GHz

Matching at 0.8 GHz, fDAC = 8847.36GSPS, straight mode

Figure 6-38 TX HD2 vs Digital Amplitude and Output Frequency at 0.85 GHz

Matching at 0.8 GHz, fDAC = 8847.36MSPS, straight mode, normalized to output power at harmonic frequency

Figure 6-40 TX HD3 vs Digital Amplitude and Output Frequency at 0.85 GHz

fDAC = 5898.24MSPS, interleave mode, 0.8 GHz matching, includes PCB and cable losses. ILn = fS/n ± fOUT.

Figure 6-42 TX Single Tone (–6 dBFS) Output Spectrum at 0.85 GHz (0-f_DAC)