米6体育平台手机版

ZHCSNB0D february 2021 – june 2023 AFE7950

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

ABJ|400
- MCBG079C
ALK|400
- MPBGAU3B

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.8 Digital Electrical Characteristics

Typical values at TA = +25°C, full temperature range is T_A,MIN = -40°C to T_J,MAX = +110°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
CML SerDes Inputs [8:1]SRX+/-
V_SRDIFF	SerDes Receiver Input Amplitude	differential	100		1200	mVpp
V_SRCOM	SerDes Input Common Mode		0.4	0.5	0.6	V
Z_SRdiff	SerDes Internal Differential Termination⁽¹⁾			100		Ω
F_SerDes	SerDes Bit Rate	Full rate mode	19		29.5	Gbps
		Half rate mode	9.5		16.25	Gbps
		Quarter rate mode	4.75		8.125	Gbps
	Insertion Loss Tolerance⁽²⁾	Serdes supply = 1.8V		25		dB
TJ	Total Jitter Tolerance				0.42	UI
CML SerDes Outputs [8:1]STX+/-
V_STDIFF	SerDes Transmitter Output Amplitude	differential	500		1000	mVpp
V_STCOM	SerDes Output Common Mode		0.4	0.45	0.55	V
Z_STdiff	SerDes Output Impedance			100		Ω
TRF	Output rise and fall time	20-80%	8			ps
TEQS	Equalization range				7	dB
TTJ	Output total jitter				0.21	UI
CMOS I/O: GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1
V_IH	High-Level Input Voltage		0.6×VDD1P8GPIO			V
V_IL	Low-Level Input Voltage				0.4×VDD1P8GPIO	V
I_IH	High-Level Input Current		–250		250	µA
I_IL	Low-Level Input Current		–250		250	µA
C_L	CMOS input capacitance			2		pF
V_OH	High-Level Ouput Voltage		VDD1P8GPIO–0.2			V
V_OL	Low-Level Output Voltage				0.2	V
Differential Inputs: SYSREF+/- Mode A
Clock_MODE				PLL Clock Mode Only
F_SYSREFMAX	SYSREF Input Frequency Maximum			40		MHz
V_SWINGSRMAX	SYSREF Input Swing Maximum			1.8		Vppdiff⁽³⁾
V_SWINGSRMIN	SYSREF Input Swing Minimum	f_REF < 500MHz		0.3		Vppdiff⁽³⁾
V_SWINGSRMIN	SYSREF Input Swing Minimum	f_REF > 500MHz		0.6		Vppdiff⁽³⁾
V_COMSRMAX	SYSREF Input Common Mode Voltage Maximum			0.8		V
V_COMSRMIN	SYSREF Input Common Mode Voltage Minimum			0.6		V
Z_T	Input termination	differential		100 ⁽¹⁾		Ω
C_L	Input capacitance	Each pin to GND		0.5		pF
LVDS Inputs: 0SYNCIN+/- and 1SYNCIN+/-
V_ICOM	Input Common Voltage			1.2		V
V_ID	Differential Input Voltage swing			450		Vppdiff⁽³⁾
Z_T	Input termination	differential		100		Ω
LVDS Outputs: 0SYNCOUT+/- and 1SYNCOUT+/-
V_OCOM	Output Common Voltage			1.2		V
V_OD	Differential Output Voltage swing			500		Vppdiff⁽³⁾
Z_T	Internal Termination			100		Ω

(1) SYSREF termination is programmable between 100Ω, 150Ω and 300Ω

(2) Loss tolerance is bump to bump from STX to SRX

(3) Vppdiff is the difference between the maximum differential voltage (positive value) and minimum differential voltage (negative value).