In SPI only mode, both FIFO buffers are accessed using register addresses. HART bus communication activity is reported to the host controller through the IRQ pin and MODEM_STATUS register. See Section 7.3.5.8 for recommended IRQ based communication techniques when using the AFEx81H1 to convert between the SPI and HART.

Write to the FIFO_U2H_WR register to enqueue the HART transmit data into FIFO_U2H. Calculate the correct parity bit and include the parity bit with the data. Do not attempt to read data from the FIFO_U2H because a read request from the FIFO_U2H_WR register is not supported. The read from the FIFO_U2H_WR register returns the data from the dequeue pointer location of FIFO_U2H, but does not dequeue the data.

Read the FIFO_H2U_RD register to dequeue the HART receive data from FIFO_H2U. If CRC is enabled and a CRC error occurs during a read request, no data are dequeued from the FIFO_H2U buffer, and the data in the readback frame are invalid. A write to the FIFO_H2U_RD register is ignored.

When communicating with the HART modem through the UART interface in SPI plus UART mode, any character received on the UARTIN pin is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the clear-to-send (CTS) response is asserted. Similarly, any character received on the RX_IN or RX_INF pin is directly enqueued into FIFO_H2U. The character is then automatically dequeued from FIFO_H2U and transmitted on UARTOUT as a normal UART character.

The FIFO buffers are accessed directly by the UART; therefore, do not use the FIFO_U2H_WR and FIFO_H2U_RD registers with the SPI. As a result of using FIFO_U2H in the data path, there is a latency from the UARTIN pin to the MOD_OUT pin; see also Section 7.3.5.6. Similarly, as a result of using FIFO_H2U, there is a latency from the RX_IN or RX_INF pin to the UARTOUT pin; see also Section 7.3.5.7.

HART bus communication activity is interfaced to the host controller through the CD and RTS pins. If the CD and RTS pins are not used, poll the MODEM_STATUS register regularly to monitor the status of the modem.

In UBM mode, any character received on the UARTIN pin that is not a part of a break command is directly enqueued into FIFO_U2H. The character is then automatically dequeued from FIFO_U2H and transmitted on the MOD_OUT pin when the CTS response is asserted. Although the UBM packets can access all registers, do not use the break command to write the HART transmit data into FIFO_U2H_WR register. Use the standard 8O1 UART character format to enqueue data into the FIFO_U2H buffer, and thus to the HART modulator.

Similarly, do not use the break command to read the HART receive data from the FIFO_H2U_RD register. HART receive data are automatically dequeued from FIFO_H2U and transmitted on UARTOUT as normal UART characters in UBM mode.