The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. Figure 8-39 shows the IRQ block diagram.

Figure 7-15 IRQ Block Diagram

There are three registers that can generate interrupts: GEN_STATUS, MODEM_STATUS, and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists.

The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky.

CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high.

When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns.

Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ, MODEM_IRQ, and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register.

If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt.

FIFO flags are not sticky; therefore, an IRQ can be triggered, but the status flag can be deasserted by the time the status information is transmitted at the output. For example, If FIFO_U2H_LEVEL_FLAG is unmasked and the FIFO_U2H level drops below the set threshold, the IRQ triggers. If the device is configured to output UBM IRQ messages and a HART data byte is received on UARTIN after the IRQ, but before the UBM captures the IRQ status, then the IRQ status and data information reads back all zeros. If UBM IRQ mode is used, wait until the IRQ message is fully transmitted on UARTOUT before putting data on UARTIN.