The HART modulator implements a look-up table (LUT) containing 128, 8-bit, signed values that represent a single-phase, continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a DAC at a clock frequency determined by the binary value of the input data. The DAC clock frequency is determined by the logical value of the data bit being transmitted. A logic 1 transmits at the internal clock frequency of 32 (default) steps times 1200 Hz. A logic 0 transmits at the internal clock frequency of 32 (default) steps times 2200 Hz. All frequencies are derived from 1.2288 MHz. This process creates the mark and space analog output signals used to represent HART data. The default mode uses 32 sinusoidal codes per period from the LUT for power savings. To generate a 128-step-per-period sinusoidal signal set MODEM_CFG.TxRES = 1. Figure 7-23 shows the HART modulator architecture.

Figure 7-18 HART Modulator Architecture