To transmit the HART data, issue a request to send (RTS) either by toggling the RTS pin low or asserting MODEM_CFG.RTS, depending on the selected communication setup. When the HART bus is available for transmission and no carrier is detected, the device deasserts the CD pin, disables the demodulator, asserts the CTS response by setting MODEM_STATUS.CTS_ASSERT = 1, and begins modulating the carrier. If the CD pin is used, wait for the CD pin to be deasserted. Otherwise, unmask CTS_ASSERT and set up the appropriate IRQs for the FIFO_U2H levels and CTS flags to enable the system controller to receive an IRQ when CTS is asserted. See also Section 7.3.5.8. When the CD pin and IRQ are not used, poll the MODEM_STATUS register regularly to detect when the CTS response is asserted.

As long as the CD pin is asserted, the demodulator remains active and the RTS request is held pending by the arbiter. Any HART transmit data bytes received by the AFEx81H1 are enqueued into FIFO_U2H, but not transmitted immediately. The system controller must monitor the FIFO_U2H level to avoid buffer overflow in this condition.

When the CTS response is asserted, the data enqueued into FIFO_U2H are dequeued and transmitted onto the MOD_OUT pin. If no data are enqueued into FIFO_U2H, the modulator starts transmitting the mark signal. The beginning of the bit stream must meet the minimum bit times requirement to make sure there is enough time for successful detection of the mark-to-space transition on the receiving side; see also Section 7.3.5.6.

The system controller is then required to maintain adequate an FIFO_U2H buffer level to avoid gap errors and deassert the RTS at the end of bit stream with the correct timing delays; see also Section 7.3.5.6.