SPRS637E February   2010  – June 2014 AM1707

PRODUCTION DATA.  

  1. 1 AM1707 ARM Microprocessor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 Memory Map Summary
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (SDRAM only)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 Reserved and No Connect
      21. 3.6.21 Supply and Ground
      22. 3.6.22 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
    4. 4.4 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    5. 4.5 Handling Ratings
    6. 4.6 Recommended Operating Conditions
    7. 4.7 Notes on Recommended Power-On Hours (POH)
    8. 4.8 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  5. 5Peripheral Information and Electrical Specifications
    1. 5.1  Parameter Information
      1. 5.1.1 Parameter Information Device-Specific Information
        1. 5.1.1.1 Signal Transition Levels
    2. 5.2  Recommended Clock and Control Signal Transition Behavior
    3. 5.3  Power Supplies
      1. 5.3.1 Power-on Sequence
      2. 5.3.2 Power-off Sequence
    4. 5.4  Reset
      1. 5.4.1 Power-On Reset (POR)
      2. 5.4.2 Warm Reset
      3. 5.4.3 Reset Electrical Data Timings
    5. 5.5  Crystal Oscillator or External Clock Input
    6. 5.6  Clock PLLs
      1. 5.6.1 PLL Device-Specific Information
      2. 5.6.2 Device Clock Generation
      3. 5.6.3 PLL Controller 0 Registers
    7. 5.7  Interrupts
      1. 5.7.1 ARM CPU Interrupts
        1. 5.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 5.7.1.2 AINTC Hardware Vector Generation
        3. 5.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 5.7.1.4 AINTC System Interrupt Assignments on the device
        5. 5.7.1.5 AINTC Memory Map
    8. 5.8  General-Purpose Input/Output (GPIO)
      1. 5.8.1 GPIO Register Description(s)
      2. 5.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 5.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    9. 5.9  EDMA
    10. 5.10 External Memory Interface A (EMIFA)
      1. 5.10.1 EMIFA Asynchronous Memory Support
      2. 5.10.2 EMIFA Synchronous DRAM Memory Support
      3. 5.10.3 EMIFA SDRAM Loading Limitations
      4. 5.10.4 EMIFA Connection Examples
      5. 5.10.5 External Memory Interface A (EMIFA) Registers
      6. 5.10.6 EMIFA Electrical Data/Timing
    11. 5.11 External Memory Interface B (EMIFB)
      1. 5.11.1 EMIFB SDRAM Loading Limitations
      2. 5.11.2 Interfacing to SDRAM
      3. 5.11.3 EMIFB Registers
      4. 5.11.4 EMIFB Electrical Data/Timing
    12. 5.12 Memory Protection Units
    13. 5.13 MMC / SD / SDIO (MMCSD)
      1. 5.13.1 MMCSD Peripheral Description
      2. 5.13.2 MMCSD Peripheral Register Description(s)
      3. 5.13.3 MMC/SD Electrical Data/Timing
    14. 5.14 Ethernet Media Access Controller (EMAC)
      1. 5.14.1 EMAC Peripheral Register Description(s)
    15. 5.15 Management Data Input/Output (MDIO)
      1. 5.15.1 MDIO Registers
      2. 5.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    16. 5.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 5.16.1 McASP Peripheral Registers Description(s)
      2. 5.16.2 McASP Electrical Data/Timing
        1. 5.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
        2. 5.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
        3. 5.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
    17. 5.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 5.17.1 SPI Peripheral Registers Description(s)
      2. 5.17.2 SPI Electrical Data/Timing
        1. 5.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 5.18 Enhanced Capture (eCAP) Peripheral
    19. 5.19 Enhanced Quadrature Encoder (eQEP) Peripheral
    20. 5.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 5.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
      2. 5.20.2 Trip-Zone Input Timing
    21. 5.21 LCD Controller
      1. 5.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 5.21.2 LCD Raster Mode
    22. 5.22 Timers
      1. 5.22.1 Timer Electrical Data/Timing
    23. 5.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 5.23.1 I2C Device-Specific Information
      2. 5.23.2 I2C Peripheral Registers Description(s)
      3. 5.23.3 I2C Electrical Data/Timing
        1. 5.23.3.1 Inter-Integrated Circuit (I2C) Timing
    24. 5.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 5.24.1 UART Peripheral Registers Description(s)
      2. 5.24.2 UART Electrical Data/Timing
    25. 5.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. 5.25.1 USB1 Unused Signal Configuration
    26. 5.26 USB0 OTG (USB2.0 OTG)
      1. 5.26.1 USB2.0 (USB0) Electrical Data/Timing
      2. 5.26.2 USB0 Unused Signal Configuration
    27. 5.27 Host-Port Interface (UHPI)
      1. 5.27.1 HPI Device-Specific Information
      2. 5.27.2 HPI Peripheral Register Description(s)
      3. 5.27.3 HPI Electrical Data/Timing
    28. 5.28 Power and Sleep Controller (PSC)
      1. 5.28.1 Power Domain and Module Topology
        1. 5.28.1.1 Power Domain States
        2. 5.28.1.2 Module States
    29. 5.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 5.29.1 PRUSS Register Descriptions
    30. 5.30 Emulation Logic
      1. 5.30.1 JTAG Port Description
      2. 5.30.2 Scan Chain Configuration Parameters
      3. 5.30.3 Initial Scan Chain Configuration
        1. 5.30.3.1 Adding TAPS to the Scan Chain
      4. 5.30.4 JTAG 1149.1 Boundary Scan Considerations
    31. 5.31 IEEE 1149.1 JTAG
      1. 5.31.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
      2. 5.31.2 JTAG Test-Port Electrical Data/Timing
    32. 5.32 Real Time Clock (RTC)
      1. 5.32.1 Clock Source
      2. 5.32.2 Registers
  6. 6Device and Documentation Support
    1. 6.1 Device Support
      1. 6.1.1 Development Support
      2. 6.1.2 Device and Development-Support Tool Nomenclature
    2. 6.2 Documentation Support
    3. 6.3 Community Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  7. 7Mechanical Packaging and Orderable Information
    1. 7.1 Thermal Data for ZKB
    2. 7.2 Packaging Information

封装选项

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机械数据 (封装 | 引脚)
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订购信息

Device Operating Conditions

4.4 Absolute Maximum Ratings Over Operating Junction Temperature Range
(Unless Otherwise Noted) (1)

Supply voltage ranges Core
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA ) (2)		 -0.5 V to 1.4 V
I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18) (2)		 -0.5 V to 2 V
I/O, 3.3V
(DVDD, USB0_VDDA33, USB1_VDDA33) (2)		 -0.5 V to 3.8V
Input voltage ranges VI I/O, 1.2V
(OSCIN, RTC_XI)		 -0.3 V to CVDD + 0.3V
VI I/O, 3.3V
(Steady State)		 -0.3V to DVDD + 0.35V
VI I/O, 3.3V
(Transient)		 DVDD + 20%
up to 20% of Signal Period
VI I/O, USB 5V Tolerant Pins:
(USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP)		 5.25V(3)
VI I/O, USB0 VBUS 5.50V(3)
Output voltage ranges VO I/O, 3.3V
(Steady State)		 -0.5 V to DVDD + 0.3V
VO I/O, 3.3V
(Transient Overshoot/Undershoot)		 20% of DVDD for up to
20% of the signal period
Clamp Current Input or Output Voltages 0.3V above or below their respective power rails. Limit clamp current that flows through the I/O's internal diode protection cells. ±20mA
Operating Junction Temperature ranges, TJ Commercial (default) 0°C to 90°C
Industrial (D version) -40°C to 90°C
Extended (A version) -40°C to 105°C
Automotive (T version) -40°C to 125°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS, RTC_VSS
(3) Up to a max of 24 hours.

4.5 Handling Ratings

UNIT
Storage temperature range, Tstg (default) -55 to 150 °C
ESD Stress Voltage, VESD(1) Human Body Model (HBM)(2) >2000 V
Charged Device Model (CDM)(3) >500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary precautions are taken. Pins listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.

4.6 Recommended Operating Conditions

MIN NOM MAX UNIT
CVDD Supply voltage, Core
(CVDD, RTC_CVDD, PLL0_VDDA)		 375 MHz version 1.14 1.2 1.32 V
456 MHz version 1.25 1.3 1.35 V
RVDD Supply Voltage, Internal RAM 375 MHz version 1.14 1.2 1.32 V
456 MHz version 1.25 1.3 1.35 V
DVDD Supply voltage, I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)		 1.71 1.8 1.89 V
Supply voltage, I/O, 3.3V
(DVDD, USB0_VDDA33, USB1_VDDA33)		 3.0 3.3 3.45 V
VSS Supply ground
(VSS, PLL0_VSSA, OSCVSS(1), RTC_VSS(1))		 0 0 0 V
VIH(2) High-level input voltage, I/O, 3.3V 2 V
High-level input voltage, OSCIN 0.7*CVDD V
High-level input voltage, RTC_XI 0.7*RTC_CVDD V
VIL(2) Low-level input voltage, I/O, 3.3V 0.8 V
Low-level input voltage, OSCIN 0.3*CVDD V
Low-level input voltage, RTC_XI 0.3*RTC_CVDD V
VHYS Input Hysteresis 160 mV
USB USB0_VBUS 4.75 5 5.25 V
tt Transition time, 10%-90%, All Inputs (unless otherwise specified in the electrical data sections) 0.25P or 10 (3) ns
FSYSCLK6 ARM Operating Frequency (SYSCLK6) Commercial (default) 0 375 (1.2V)
456 (1.3V)		 MHz
Industrial (D suffix) 0 456 (1.3V) MHz
Extended (A suffix) 0 375(1.2V) MHz
Automotive (T suffix) 0 375 (1.2V) MHz
(1) When an external crystal is used, oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(2) Unless specifically indicated, these I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification. USB1 I/Os adhere to USB1.1 specification.
(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.

4.7 Notes on Recommended Power-On Hours (POH)

The information in the section below is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.

To avoid significant degradation, the device power-on hours (POH) must be limited to the following:

Table 4-1 Recommended Power-On Hours

Silicon Revision Speed Grade Operating Junction Temperature (Tj) Nominal CVDD Voltage (V) Power-On Hours [POH] (hours)
D 375 MHz 0 to 90 °C 1.2V 100,000
D 375 MHz -40 to 105 °C 1.2V 75,000(1)
D 375 MHz -40 to 125 °C 1.2V 20,000
D 456 MHz 0 to 90 °C 1.3V 100,000
D 456 MHz -40 to 90 °C 1.3V 100,000
(1) 100,000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz.

Note: Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.

The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI’s standard terms and conditions for TI semiconductor products.

4.8 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH(4) High-level output voltage (3.3V I/O) DVDD= 3.15V, IOH = -4 mA 2.4 V
DVDD= 3.15V, IOH = 100 μA 2.95 V
VOL(4) Low-level output voltage (3.3V I/O) DVDD= 3.15V, IOL = 4mA 0.4 V
DVDD= 3.15V, IOL = -100 μA 0.2 V
II(2)(4) Input current VI = VSS to DVDD without opposing internal resistor ±35 μA
VI = VSS to DVDD with opposing internal pullup resistor (1) -30 -200 μA
VI = VSS to DVDD with opposing internal pulldown resistor (1) 50 300 μA
VI = VSS to USB1_VDDA33 -
USB1_DM and USB1_DP		 ±40 μA
IOH(4) High-level output current -4 mA
IOL(4) Low-level output current 4 mA
IOZ(3) I/O Off-state output current VO = VDD or VSS; Internal pull disabled ±35 μA
CI Input capacitance LVCMOS signals 3 pF
OSCIN and RTC_XI 2 pF
CO Output capacitance LVCMOS signals 3 pF
(1) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(4) These I/O specifications apply to regular 3.3V IOs and do not apply to USB0 and USB1 unless specifically indicated. USB0 I/Os adhere to the USB 2.0 specification. USB1 I/Os adhere to the USB 1.1 specification.
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