SPRS658F February   2010  – March 2014 AM1806

PRODUCTION DATA.  

  1. 1 AM1806 ARM Microprocessor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 Memory Map Summary
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Memory Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  Programmable Real-Time Unit (PRU)
      9. 3.7.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.7.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.7.11 Boot
      12. 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.7.14 Timers
      15. 3.7.15 Multichannel Audio Serial Ports (McASP)
      16. 3.7.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.7.17 Universal Serial Bus Modules (USB0)
      18. 3.7.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.7.19 Liquid Crystal Display Controller(LCD)
      20. 3.7.20 Universal Host-Port Interface (UHPI)
      21. 3.7.21 Universal Parallel Port (uPP)
      22. 3.7.22 Video Port Interface (VPIF)
      23. 3.7.23 General Purpose Input Output
      24. 3.7.24 Reserved and No Connect
      25. 3.7.25 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Module States
    9. 6.9  EDMA
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 External Memory Interface Register Descriptions
      5. 6.10.5 EMIFA Electrical Data/Timing
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 MDDR/DDR2 Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Multichannel Audio Serial Port (McASP)
      1. 6.14.1 McASP Peripheral Registers Description(s)
      2. 6.14.2 McASP Electrical Data/Timing
        1. 6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
    15. 6.15 Multichannel Buffered Serial Port (McBSP)
      1. 6.15.1 McBSP Peripheral Register Description(s)
      2. 6.15.2 McBSP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing
    16. 6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.16.1 SPI Peripheral Registers Description(s)
      2. 6.16.2 SPI Electrical Data/Timing
        1. 6.16.2.1 Serial Peripheral Interface (SPI) Timing
    17. 6.17 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.17.1 I2C Device-Specific Information
      2. 6.17.2 I2C Peripheral Registers Description(s)
      3. 6.17.3 I2C Electrical Data/Timing
        1. 6.17.3.1 Inter-Integrated Circuit (I2C) Timing
    18. 6.18 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.18.1 UART Peripheral Registers Description(s)
      2. 6.18.2 UART Electrical Data/Timing
    19. 6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.19.1 USB Peripheral Registers Description(s)
      2. 6.19.2 USB0 [USB2.0] Electrical Data/Timing
    20. 6.20 LCD Controller (LCDC)
      1. 6.20.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.20.2 LCD Raster Mode
    21. 6.21 Host-Port Interface (UHPI)
      1. 6.21.1 HPI Device-Specific Information
      2. 6.21.2 HPI Peripheral Register Description(s)
      3. 6.21.3 HPI Electrical Data/Timing
    22. 6.22 Universal Parallel Port (uPP)
      1. 6.22.1 uPP Register Descriptions
      2. 6.22.2 uPP Electrical Data/Timing
    23. 6.23 Video Port Interface (VPIF)
      1. 6.23.1 VPIF Register Descriptions
      2. 6.23.2 VPIF Electrical Data/Timing
    24. 6.24 Enhanced Capture (eCAP) Peripheral
    25. 6.25 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.25.1 eHRPWM Register Descriptions
      2. 6.25.2 Enhanced Pulse Width Modulator (eHRPWM) Timing
      3. 6.25.3 Trip-Zone Input Timing
    26. 6.26 Timers
      1. 6.26.1 Timer Electrical Data/Timing
    27. 6.27 Real Time Clock (RTC)
      1. 6.27.1 Clock Source
      2. 6.27.2 Real-Time Clock Register Descriptions
    28. 6.28 General-Purpose Input/Output (GPIO)
      1. 6.28.1 GPIO Register Description(s)
      2. 6.28.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.28.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 Initial Scan Chain Configuration
        1. 6.30.3.1 Adding TAPS to the Scan Chain
      4. 6.30.4 IEEE 1149.1 JTAG
        1. 6.30.4.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
        2. 6.30.4.2 JTAG Test-Port Electrical Data/Timing
      5. 6.30.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZCE|361
  • ZWT|361
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Mechanical Packaging and Orderable Information

This section describes the device orderable part numbers, packaging options, materials, thermal and mechanical parameters.

8.1 Thermal Data for ZCE Package

The following table(s) show the thermal resistance characteristics for the PBGA–ZCE mechanical package.

Table 8-1 Thermal Resistance Characteristics (PBGA Package) [ZCE]

NO. °C/W(1) AIR FLOW (m/s)(2)
1 RΘJC Junction-to-case 7.6 N/A
2 RΘJB Junction-to-board 11.3 N /A
3 RΘJA Junction-to-free air 23.9 0.00
4 RΘJMA Junction-to-moving air 21.2 0.50
5 20.3 1.00
6 19.5 2.00
7 18.6 4.00
8 PsiJT Junction-to-package top 0.2 0.00
9 0.3 0.50
10 0.3 1.00
11 0.4 2.00
12 0.5 4.00
13 PsiJB Junction-to-board 11.2 0.00
14 11.1 0.50
15 11.1 1.00
16 11.0 2.00
17 10.9 4.00
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. Power dissipation of 500 mW and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness
(2) m/s = meters per second

8.2 Thermal Data for ZWT Package

The following table(s) show the thermal resistance characteristics for the PBGA–ZWT mechanical package.

Table 8-2 Thermal Resistance Characteristics (PBGA Package) [ZWT]

NO. °C/W(1) AIR FLOW (m/s)(2)
1 RΘJC Junction-to-case 7.3 N/A
2 RΘJB Junction-to-board 12.4 N /A
3 RΘJA Junction-to-free air 23.7 0.00
4 RΘJMA Junction-to-moving air 21.0 0.50
5 20.1 1.00
6 19.3 2.00
7 18.4 4.00
8 PsiJT Junction-to-package top 0.2 0.00
9 0.3 0.50
10 0.3 1.00
11 0.4 2.00
12 0.5 4.00
13 PsiJB Junction-to-board 12.3 0.00
14 12.2 0.50
15 12.1 1.00
16 12.0 2.00
17 11.9 4.00
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and 1.5oz (50um) inner copper thickness
(2) m/s = meters per second
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