SPRS709D November   2010  – March 2014 AM1810

PRODUCTION DATA.  

  1. 1 AM1810 ARM Microprocessor For PROFIBUS
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 ARM Subsystem
      1. 3.3.1 ARM926EJ-S RISC CPU
      2. 3.3.2 CP15
      3. 3.3.3 MMU
      4. 3.3.4 Caches and Write Buffer
      5. 3.3.5 Advanced High-Performance Bus (AHB)
      6. 3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
      7. 3.3.7 ARM Memory Mapping
    4. 3.4 Memory Map Summary
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Memory Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  PROFIBUS Real-Time Unit (PRU)
      9. 3.7.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.7.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.7.11 Boot
      12. 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.7.14 Timers
      15. 3.7.15 Multichannel Audio Serial Ports (McASP)
      16. 3.7.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.7.17 Universal Serial Bus Modules (USB0, USB1)
      18. 3.7.18 Ethernet Media Access Controller (EMAC)
      19. 3.7.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.7.20 Liquid Crystal Display Controller(LCD)
      21. 3.7.21 Serial ATA Controller (SATA)
      22. 3.7.22 Universal Host-Port Interface (UHPI)
      23. 3.7.23 Universal Parallel Port (uPP)
      24. 3.7.24 Video Port Interface (VPIF)
      25. 3.7.25 General Purpose Input Output
      26. 3.7.26 Reserved and No Connect
      27. 3.7.27 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 ARM CPU Interrupts
        1. 6.7.1.1 ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
        2. 6.7.1.2 AINTC Hardware Vector Generation
        3. 6.7.1.3 AINTC Hardware Interrupt Nesting Support
        4. 6.7.1.4 AINTC System Interrupt Assignments
        5. 6.7.1.5 AINTC Memory Map
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Module States
    9. 6.9  EDMA
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 External Memory Interface Register Descriptions
      5. 6.10.5 EMIFA Electrical Data/Timing
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 MDDR/DDR2 Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
    14. 6.14 Serial ATA Controller (SATA)
      1. 6.14.1 SATA Register Descriptions
      2. 6.14.2 SATA Interface
        1. 6.14.2.1 SATA Interface Schematic
        2. 6.14.2.2 Compatible SATA Components and Modes
        3. 6.14.2.3 PCB Stackup Specifications
        4. 6.14.2.4 Routing Specifications
        5. 6.14.2.5 Coupling Capacitors
        6. 6.14.2.6 SATA Interface Clock Source requirements
      3. 6.14.3 SATA Unused Signal Configuration
    15. 6.15 Multichannel Audio Serial Port (McASP)
      1. 6.15.1 McASP Peripheral Registers Description(s)
      2. 6.15.2 McASP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
    16. 6.16 Multichannel Buffered Serial Port (McBSP)
      1. 6.16.1 McBSP Peripheral Register Description(s)
      2. 6.16.2 McBSP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Buffered Serial Port (McBSP) Timing
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
    18. 6.18 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.18.1 I2C Device-Specific Information
      2. 6.18.2 I2C Peripheral Registers Description(s)
      3. 6.18.3 I2C Electrical Data/Timing
        1. 6.18.3.1 Inter-Integrated Circuit (I2C) Timing
    19. 6.19 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.19.1 UART Peripheral Registers Description(s)
      2. 6.19.2 UART Electrical Data/Timing
    20. 6.20 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.20.1 USB Peripheral Registers Description(s)
      2. 6.20.2 USB0 [USB2.0] Electrical Data/Timing
    21. 6.21 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]
    22. 6.22 Ethernet Media Access Controller (EMAC)
      1. 6.22.1 EMAC Peripheral Register Description(s)
      2. 6.22.2 EMAC Electrical Data/Timing
    23. 6.23 Management Data Input/Output (MDIO)
      1. 6.23.1 MDIO Registers
      2. 6.23.2 Management Data Input/Output (MDIO) Electrical Data/Timing
    24. 6.24 LCD Controller (LCDC)
      1. 6.24.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.24.2 LCD Raster Mode
    25. 6.25 Host-Port Interface (UHPI)
      1. 6.25.1 HPI Device-Specific Information
      2. 6.25.2 HPI Peripheral Register Description(s)
      3. 6.25.3 HPI Electrical Data/Timing
    26. 6.26 Universal Parallel Port (uPP)
      1. 6.26.1 uPP Register Descriptions
      2. 6.26.2 uPP Electrical Data/Timing
    27. 6.27 Video Port Interface (VPIF)
      1. 6.27.1 VPIF Register Descriptions
      2. 6.27.2 VPIF Electrical Data/Timing
    28. 6.28 Enhanced Capture (eCAP) Peripheral
    29. 6.29 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.29.1 eHRPWM Register Descriptions
      2. 6.29.2 Enhanced Pulse Width Modulator (eHRPWM) Timing
      3. 6.29.3 Trip-Zone Input Timing
    30. 6.30 Timers
      1. 6.30.1 Timer Electrical Data/Timing
    31. 6.31 Real Time Clock (RTC)
      1. 6.31.1 Clock Source
      2. 6.31.2 Real-Time Clock Register Descriptions
    32. 6.32 General-Purpose Input/Output (GPIO)
      1. 6.32.1 GPIO Register Description(s)
      2. 6.32.2 GPIO Peripheral Input/Output Electrical Data/Timing
      3. 6.32.3 GPIO Peripheral External Interrupts Electrical Data/Timing
    33. 6.33 Programmable Real-Time Unit Subsystem (PRUSS) With PROFIBUS
      1. 6.33.1 PRUSS Register Descriptions
    34. 6.34 Emulation Logic
      1. 6.34.1 JTAG Port Description
      2. 6.34.2 Scan Chain Configuration Parameters
      3. 6.34.3 Initial Scan Chain Configuration
        1. 6.34.3.1 Adding TAPS to the Scan Chain
      4. 6.34.4 IEEE 1149.1 JTAG
        1. 6.34.4.1 JTAG Peripheral Register Description(s) - JTAG ID Register (DEVIDR0)
        2. 6.34.4.2 JTAG Test-Port Electrical Data/Timing
      5. 6.34.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZWT Package

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZWT|361
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range
(Unless Otherwise Noted) (1)

Supply voltage ranges Core Logic, Variable and Fixed
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA , PLL1_VDDA , SATA_VDD, USB_CVDD ) (2)		 -0.5 V to 1.4 V
I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18, SATA_VDDR, DDR_DVDD18) (2)		 -0.5 V to 2 V
I/O, 3.3V
(DVDD3318_A, DVDD3318_B, DVDD3318_C, USB0_VDDA33, USB1_VDDA33) (2)		 -0.5 V to 3.8V
Input voltage (VI) ranges Oscillator inputs (OSCIN, RTC_XI), 1.2V -0.3 V to CVDD + 0.3V
Dual-voltage LVCMOS inputs, 3.3V or 1.8V (Steady State) -0.3V to DVDD + 0.3V
Dual-voltage LVCMOS inputs, operated as 3.3V
(Transient Overshoot/Undershoot)		 DVDD + 20%
up to 20% of Signal Period
Dual-voltage LVCMOS inputs, operated as 1.8V
(Transient Overshoot/Undershoot)		 DVDD + 30%
up to 30% of Signal Period
USB 5V Tolerant IOs:
(USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP)		 5.25V(3)
USB0 VBUS Pin 5.50V(3)
Output voltage (VO) ranges Dual-voltage LVCMOS outputs, 3.3V or 1.8V
(Steady State)		 -0.3 V to DVDD + 0.3V
Dual-voltage LVCMOS outputs, operated as 3.3V
(Transient Overshoot/Undershoot)		 DVDD + 20%
up to 20% of Signal Period
Dual-voltage LVCMOS outputs, operated as 1.8V
(Transient Overshoot/Undershoot)		 DVDD + 30%
up to 30% of Signal Period
Clamp Current Input or Output Voltages 0.3V above or below their respective power rails. Limit clamp current that flows through the I/O's internal diode protection cells. ±20mA
Operating Junction Temperature ranges, TJ Extended -40°C to 105°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS
(3) Up to a maximum of 24 hours.

5.2 Handling Ratings

MIN MAX UNIT
Storage temperature range, Tstg (default) -55 150 °C
ESD Stress Voltage, VESD(1) Human Body Model (HBM) (2) >1 >1 kV
Charged Device Model (CDM) (3) >500 >500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP 155 states that 500V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary precautions are taken. Pins listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP 157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.

5.3 Recommended Operating Conditions

NAME DESCRIPTION CONDITION MIN NOM MAX UNIT
Supply
Voltage		 CVDD Core Logic Supply Voltage (variable) 1.2V operating point 1.14 1.2 1.32 V
1.1V operating point 1.05 1.1 1.16 V
1.0V operating point 0.95 1.0 1.05 V
RVDD Internal RAM Supply Voltage 375 MHz versions 1.14 1.2 1.32 V
RTC_CVDD (4) RTC Core Logic Supply Voltage 0.9 1.2 1.32 V
PLL0_VDDA PLL0 Supply Voltage 1.14 1.2 1.32 V
PLL1_VDDA PLL1 Supply Voltage 1.14 1.2 1.32 V
SATA_VDD SATA Core Logic Supply Voltage 1.14 1.2 1.32 V
USB_CVDD USB0, USB1 Core Logic Supply Voltage 1.14 1.2 1.32 V
USB0_VDDA18 USB0 PHY Supply Voltage 1.71 1.8 1.89 V
USB0_VDDA33 USB0 PHY Supply Voltage 3.15 3.3 3.45 V
USB1_VDDA18 USB1 PHY Supply Voltage 1.71 1.8 1.89 V
USB1_VDDA33 USB1 PHY Supply Voltage 3.15 3.3 3.45 V
DVDD18(5) 1.8V Logic Supply 1.71 1.8 1.89 V
SATA_VDDR SATA PHY Internal Regulator Supply Voltage 1.71 1.8 1.89 V
DDR_DVDD18 (5) DDR2 PHY Supply Voltage 1.71 1.8 1.89 V
DDR_VREF DDR2/mDDR reference voltage 0.49*
DDR_DVDD18		 0.5*
DDR_DVDD18		 0.51*
DDR_DVDD18		 V
DDR_ZP DDR2/mDDR impedance control,
connected via 50Ω resistor to Vss		 Vss V
DVDD3318_A Power Group A Dual-voltage IO Supply Voltage 1.8V operating point 1.71 1.8 1.89 V
3.3V operating point 3.15 3.3 3.45 V
DVDD3318_B Power Group B Dual-voltage IO Supply Voltage 1.8V operating point 1.71 1.8 1.89 V
3.3V operating point 3.15 3.3 3.45 V
DVDD3318_C Power Group C Dual-voltage IO Supply Voltage 1.8V operating point 1.71 1.8 1.89 V
3.3V operating point 3.15 3.3 3.45 V
Supply
Ground		 VSS Core Logic Digital Ground V
PLL0_VSSA PLL0 Ground V
PLL1_VSSA PLL1 Ground V
SATA_VSS SATA PHY Ground 0 0 0 V
OSCVSS(1) Oscillator Ground V
RTC_VSS(1) RTC Oscillator Ground V
USB0_VSSA USB0 PHY Ground V
USB0_VSSA33 USB0 PHY Ground V
Voltage
Input High		 VIH High-level input voltage, Dual-voltage I/O, 3.3V(2) 2 V
High-level input voltage, Dual-voltage I/O, 1.8V (2) 0.65*DVDD V
High-level input voltage, RTC_XI 0.8*RTC_CVDD V
High-level input voltage, OSCIN 0.8*CVDD V
Voltage
Input Low		 VIL Low-level input voltage, Dual-voltage I/O, 3.3V(2) 0.8 V
Low-level input voltage, Dual-voltage I/O, 1.8V (2) 0.35*DVDD V
Low-level input voltage, RTC_XI 0.2*RTC_CVDD V
Low-level input voltage, OSCIN 0.2*CVDD V
USB USB0_VBUS USB external charge pump input 0 5.25 V
Differential Clock Input Voltage Differential input voltage, SATA_REFCLKP and SATA_REFCLKN 250 2000 mV
Transition Time tt Transition time, 10%-90%, All Inputs (unless otherwise specified in the electrical data sections) 0.25P or 10 (3) ns
Operating
Frequency		 FPLL0_SYSCLK6 Extended temperature grade (A suffix) CVDD = 1.2V operating point 0 375 MHz
CVDD = 1.1V operating point 0 200
CVDD = 1.0V operating point 0 100
(1) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(2) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard.
(3) Whichever is smaller. Where P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.
(4) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD. If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(5) DVDD18 must be powered even if all of the DVDD3318_x supplies are operated at 3.3V.

5.4 Notes on Recommended Power-On Hours (POH)

The information in the section below is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.

To avoid significant degradation, the device power-on hours (POH) must be limited to the following:

Table 5-1 Recommended Power-On Hours

Silicon Revision Speed Grade Operating Junction Temperature (Tj) Nominal CVDD Voltage (V) Power-On Hours [POH] (hours)
A 300 MHz 0 to 90 °C 1.2V 100,000
B/E 300 MHz 0 to 90 °C 1.2V 100,000
B/E 375 MHz 0 to 90 °C 1.2V 100,000
B/E 375 MHz -40 to 105 °C 1.2V 75,000(1)
B/E 456 MHz 0 to 90 °C 1.3V 100,000
B/E 456 MHz -40 to 90 °C 1.3V 100,000
(1) 100,000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz

Note: Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.

The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under TI’s standard terms and conditions for TI semiconductor products.

5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage
(dual-voltage LVCMOS IOs at 3.3V)(3)		 DVDD= 3.15V, IOH = -4 mA 2.4 V
DVDD= 3.15V, IOH = -100 μA 2.95 V
High-level output voltage
(dual-voltage LVCMOS IOs at 1.8V)(3)		 DVDD= 1.71V, IOH = -2 mA DVDD-0.45 V
VOL Low-level output voltage
(dual-voltage LVCMOS I/Os at 3.3V)		 DVDD= 3.15V, IOL = 4mA 0.4 V
DVDD= 3.15V, IOL = 100 μA 0.2 V
Low-level output voltage
(dual-voltage LVCMOS I/Os at 1.8V)		 DVDD= 1.71V, IOL = 2mA 0.45 V
II(2) Input current(3)
(dual-voltage LVCMOS I/Os)		 VI = VSS to DVDD without opposing internal resistor ±9 μA
VI = VSS to DVDD with opposing internal pullup resistor (1) 70 310 μA
VI = VSS to DVDD with opposing internal pulldown resistor (1) -75 -270 μA
Input current (DDR2/mDDR I/Os) VI = VSS to DVDD with opposing internal pulldown resistor (1) -77 -286 μA
IOH High-level output current(3)
(dual-voltage LVCMOS I/Os)		 -6 mA
IOL Low-level output current(3)
(dual-voltage LVCMOS I/Os)		 6 mA
Capacitance Input capacitance (dual-voltage LVCMOS) 3 pF
Output capacitance (dual-voltage LVCMOS) 3 pF
(1) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. The pull-up and pull-down strengths shown represent the minimum and maximum strength across process variation.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard. USB0 I/Os adhere to the USB2.0 standard. USB1 I/Os adhere to the USB1.1 standard. SATA I/Os adhere to the SATA-I and SATA-II standards.
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