米6体育平台手机版

ZHCSQ84D october 2022 – july 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1
1 特性
2 应用
3 说明
1. 3.1 功能方框图
4 Revision History
5 Device Comparison
1. 5.1 Related Products
6 Terminal Configuration and Functions
1. 6.1 Pin Diagram
  1. 6.1.1 ZCZ Pin Diagram
2. 6.2 Pin Attributes
  1. 13
  2. 14
3. 6.3 Signal Descriptions
  1. 16
  2. 6.3.1 ADC
    1. 18
    2. 19
    3. 20
    4. 21
    5. 22
    6. 6.3.1.1 ADC-CMPSS Signal Connections
  3. 6.3.2 ADC_CAL
    1. 25
  4. 6.3.3 ADC VREF
    1. 27
  5. 6.3.4 CPSW
    1. 29
    2. 30
    3. 31
    4. 32
    5. 33
    6. 34
    7. 35
  6. 6.3.5 CPTS
    1. 37
  7. 6.3.6 DAC
    1. 39
  8. 6.3.7 Emulation and Debug
    1. 41
    2. 42
  9. 6.3.8 EPWM
    1. 44
    2. 45
    3. 46
    4. 47
    5. 48
    6. 49
    7. 50
    8. 51
    9. 52
    10. 53
    11. 54
    12. 55
    13. 56
    14. 57
    15. 58
    16. 59
    17. 60
    18. 61
    19. 62
    20. 63
    21. 64
    22. 65
    23. 66
    24. 67
    25. 68
    26. 69
    27. 70
    28. 71
    29. 72
    30. 73
    31. 74
    32. 75
  10. 6.3.9 EQEP
    1. 77
    2. 78
    3. 79
  11. 6.3.10 FSI
    1. 81
    2. 82
    3. 83
    4. 84
    5. 85
    6. 86
    7. 87
    8. 88
  12. 6.3.11 GPIO
    1. 90
  13. 6.3.12 GPMC
    1. 92
  14. 6.3.13 I2C
    1. 94
    2. 95
    3. 96
    4. 97
    5. 98
  15. 6.3.14 LIN
    1. 100
    2. 101
    3. 102
    4. 103
    5. 104
  16. 6.3.15 MCAN
    1. 106
    2. 107
    3. 108
    4. 109
  17. 6.3.16 SPI (MCSPI)
    1. 111
    2. 112
    3. 113
    4. 114
    5. 115
  18. 6.3.17 MMC
    1. 117
  19. 6.3.18 Power Supply
    1. 119
  20. 6.3.19 PRU-ICSS
    1. 121
    2. 122
    3. 123
    4. 124
    5. 125
  21. 6.3.20 QSPI
    1. 127
  22. 6.3.21 Reserved
    1. 129
  23. 6.3.22 SDFM
    1. 131
    2. 132
  24. 6.3.23 System and Miscellaneous
    1. 6.3.23.1 Boot Mode Configuration
      1. 135
    2. 6.3.23.2 Clocking
      1. 137
      2. 138
      3. 139
    3. 6.3.23.3 SYSTEM
      1. 141
    4. 6.3.23.4 VMON
      1. 143
  25. 6.3.24 UART
    1. 145
    2. 146
    3. 147
    4. 148
    5. 149
    6. 150
  26. 6.3.25 XBAR
    1. 152
4. 6.4 Pin Connectivity Requirements
7 Specifications
8 Detailed Description
1. 8.1 Overview
2. 8.2 Processor Subsystems
  1. 8.2.1 Arm Cortex-R5F Subsystem
9 Applications, Implementation, and Layout
1. 9.1 Device Connection and Layout Fundamentals
10Device and Documentation Support
11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

ZCZ|324

散热焊盘机械数据 (封装 | 引脚)

订购信息

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-30 GPMC and NOR Flash — Asynchronous Read — Single Word

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-31 GPMC and NOR Flash — Asynchronous Read — 32–Bit

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.

C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field.

D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-32 GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 7-33 GPMC and NOR Flash — Asynchronous Write — Single Word

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 7-34 GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 7-35 GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word