ZHCSVF3P
December 1990 – March 2024
AM26C31
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics: AM26C31C and AM26C31I
5.6
Electrical Characteristics: AM26C31Q and AM26C31M
5.7
Switching Characteristics: AM26C31C and AM26C31I
5.8
Switching Characteristics: AM26C31Q and AM26C31M
5.9
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
Active-High and Active-Low
7.3.2
Operates From a Single 5V Supply
7.4
Device Functional Modes
8
Application Information Disclaimer
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
接收文档更新通知
9.2
支持资源
9.3
Trademarks
9.4
静电放电警告
9.5
术语表
10
Revision History
11
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
N|16
MPDI002C
PW|16
MPDS361A
DB|16
MPDS507A
D|16
MPDS178G
NS|16
MPDS551A
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsvf3p_oa
zhcsvf3p_pm
6
Parameter Measurement Information
Figure 6-1
Differential and Common-Mode Output Voltages
A.
C1, C2, and C3 include probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, duty cycle ≤ 50%, and t
r
, t
f
≤ 6ns.
Figure 6-2
Propagation Delay Time and Skew Waveforms and Test Circuit
A.
C1, C2, and C3 include probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, duty cycle ≤ 50%, and t
r
, t
f
≤ 6ns.
Figure 6-3
Differential-Output Rise and Fall-Time Waveforms and Test Circuit
A.
C1, C2, and C3 include probe and jig capacitance.
B.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, duty cycle ≤ 50%, and t
r
, t
f
≤ 6ns.
C.
Each enable is tested separately.
Figure 6-4
Output Enable and Disable Time Waveforms and Test Circuit
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