ZHCSPJ8B December   2021  – December 2023 AM2732 , AM2732-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM273x ZCE Pin Diagram
      2. 5.1.2 AM273x NZN Pin Diagram
    2. 5.2 Pin Attributes (AM273x ZCE, NZN Packages)
      1.      13
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC Signal Descriptions
        1.       16
      2. 5.3.2  CPTS Signal Descriptions
        1.       18
      3. 5.3.3  CSI 2.0 Signal Descriptions
        1.       20
      4. 5.3.4  DMM Signal Descriptions
        1.       22
      5. 5.3.5  ECAP Signal Descriptions
        1.       24
      6. 5.3.6  EPWM Signal Descriptions
        1.       26
        2.       27
        3.       28
        4.       29
      7. 5.3.7  GPIO Signal Descriptions
        1.       31
        2.       32
      8. 5.3.8  I2C Signal Descriptions
        1.       34
        2.       35
        3.       36
      9. 5.3.9  Clock Signal Descriptions
        1.       38
        2.       39
      10. 5.3.10 JTAG Signal Descriptions
        1.       41
      11. 5.3.11 LVDS Signal Descriptions
        1.       43
      12. 5.3.12 MCAN Signal Descriptions
        1.       45
        2.       46
      13. 5.3.13 MCASP Signal Descriptions
        1.       48
        2.       49
        3.       50
      14. 5.3.14 Ethernet Signal Descriptions
        1.       52
        2.       53
        3.       54
        4.       55
      15. 5.3.15 GPIO Signal Descriptions
        1.       57
        2.       58
      16. 5.3.16 Power Supply Signal Descriptions
        1.       60
      17. 5.3.17 QSPI Signal Descriptions
        1.       62
      18. 5.3.18 Reserverd Signal Descriptions
        1.       64
      19. 5.3.19 UART Signal Descriptions
        1.       66
        2.       67
      20. 5.3.20 SPI Signal Descriptions
        1.       69
        2.       70
        3.       71
        4.       72
      21. 5.3.21 System Signal Descriptions
        1.       74
      22. 5.3.22 Trace Signal Descriptions
        1.       76
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - Automotive
    3. 6.3  Power-On Hours (POH)
      1. 6.3.1 Automotive Temperature Profile
      2. 6.3.2 Industrial Temperature Profile
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Supply Specifications
    7. 6.7  I/O Buffer Type and Voltage Rail Dependency
    8. 6.8  CPU Specifications
    9. 6.9  Thermal Resistance Characteristics for nFBGA Package [ZCE285A]
    10. 6.10 Thermal Resistance Characteristics for nFBGA Package [NZN225A]
    11. 6.11 Power Consumption Summary
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Power Supply Sequencing and Reset Timing
      2. 6.12.2 Clock Specifications
      3. 6.12.3 Peripheral Information
        1. 6.12.3.1  QSPI Flash Memory Peripheral
          1. 6.12.3.1.1 QSPI Timing Conditions
          2. 6.12.3.1.2 QSPI Timing Requirements
          3. 6.12.3.1.3 QSPI Switching Characteristics
        2. 6.12.3.2  MIBSPI Peripheral
          1. 6.12.3.2.1 SPI Timing Conditions
          2. 6.12.3.2.2 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 6.12.3.2.3 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. 6.12.3.2.4 SPI Slave Mode Timing and Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        3. 6.12.3.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
          1. 6.12.3.3.1  RGMII/GMII/MII Timing Conditions
          2. 6.12.3.3.2  RGMII Transmit Clock Switching Characteristics
          3. 6.12.3.3.3  RGMII Transmit Data and Control Switching Characteristics
          4. 6.12.3.3.4  RGMII Recieve Clock Timing Requirements
          5. 6.12.3.3.5  RGMII Recieve Data and Control Timing Requirements
          6. 6.12.3.3.6  RMII Transmit Clock Switching Characteristics
          7. 6.12.3.3.7  RMII Transmit Data and Control Switching Characteristics
          8. 6.12.3.3.8  RMII Receive Clock Timing Requirements
          9. 6.12.3.3.9  RMII Receive Data and Control Timing Requirements
          10. 6.12.3.3.10 MII Transmit Switching Characteristics
          11. 6.12.3.3.11 MII Receive Clock Timing Requirements
          12. 6.12.3.3.12 MII Receive Timing Requirements
          13. 6.12.3.3.13 MII Transmit Clock Timing Requirements
          14. 6.12.3.3.14 MDIO Interface Timings
        4. 6.12.3.4  LVDS/Aurora Instrumentation and Measurement Peripheral
          1. 6.12.3.4.1 LVDS Interface Configuration
          2. 6.12.3.4.2 LVDS Interface Timings
        5. 6.12.3.5  UART Peripheral
          1. 6.12.3.5.1 UART Timing Requirements
        6. 6.12.3.6  I2C Protocol Definition
          1. 6.12.3.6.1 I2C Timing Requirements #GUID-D615B3D8-5F52-430D-93CB-70204118ACE4/T4362547-185
        7. 6.12.3.7  Controller Area Network - Flexible Data-Rate (CAN-FD)
          1. 6.12.3.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
        8. 6.12.3.8  CSI-2 Peripheral
        9. 6.12.3.9  General Purpose ADC (GPADC)
        10. 6.12.3.10 Enhanced Pulse-Width Modulator (ePWM)
        11. 6.12.3.11 Enhanced Capture (eCAP)
        12. 6.12.3.12 General-Purpose Input/Output
          1. 6.12.3.12.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-1BEBEADE-CEC6-42DA-A124-5081550EEDD7/T4362547-45 #GUID-1BEBEADE-CEC6-42DA-A124-5081550EEDD7/T4362547-50
      4. 6.12.4 Emulation and Debug
        1. 6.12.4.1 Emulation and Debug Description
        2. 6.12.4.2 JTAG Interface
          1. 6.12.4.2.1 Timing Requirements for IEEE 1149.1 JTAG
          2. 6.12.4.2.2 Switching Characteristics for IEEE 1149.1 JTAG
        3. 6.12.4.3 ETM Trace Interface
          1. 6.12.4.3.1 ETM TRACE Timing Requirements
          2. 6.12.4.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Main Subsystem
    3. 7.3 DSP Subsystem
    4. 7.4 Radar Control Subsystem
    5. 7.5 Other Subsystems
      1. 7.5.1 Radar A2D Data Format Over CSI2 Interface
      2. 7.5.2 ADC Channels (Service) for User Application
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Schematic
      2. 8.1.2 Layout
        1. 8.1.2.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • NZN|225
  • ZCE|285
散热焊盘机械数据 (封装 | 引脚)
订购信息
6.12.3.3.5 RGMII Recieve Data and Control Timing Requirements
NO.PARAMETERDESCRIPTIONMINMAXUNIT
5tsu(RXD-RXCH)Setup time, receive selected signals valid before MSS_RGMII_RCLK high/low2ns
6th(RXCH-RXD)Hold time, receive selected signals valid after MSS_RGMII_RCLK high/low2ns
GUID-A6C959E5-ABF8-4A8F-96A7-5B98A8BAEA9B-low.gif
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. MSS_RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
Figure 6-12 GMAC Receive Interface Timing, RGMIIn operation
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