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ZHCS488K October 2011 – December 2018 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

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ZCZ|324

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7.7.2.3.6.2 DQS[x] and DQ[x] Routing Specification

Skew within the DQS[x] and DQ[x] net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. DQLMn is defined as DQ Longest Manhattan distance n, where n is the byte number. For a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.

NOTE

Matching the lengths across all bytes is not required, nor is it recommended. Length matching is only required within each byte.

Given the DQS[x] and DQ[x] pin locations on the AM335x device and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 7-67 shows this distance for a two-load case. It is from this distance that the specifications on the lengths of the transmission lines for the data bus are determined. For DQS[x] and DQ[x] routing, these specifications are contained in Table 7-69.

AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 dqlm_sprs717.gif

There are two DQLMs, one for each byte (16-bit interface). Each DQLM is the longest Manhattan distance of the byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1

Figure 7-67 DQLM for Any Number of Allowed DDR3 Devices

Table 7-69 DQS[x] and DQ[x] Routing Specification⁽¹⁾⁽²⁾

NO.	PARAMETER	MIN	MAX	UNIT
1	DQ0 nominal length⁽³⁾⁽⁴⁾		DQLM0	mils
2	DQ1 nominal length⁽³⁾⁽⁵⁾		DQLM1	mils
3	DQ[x] skew⁽⁶⁾		25	mils
4	DQS[x] skew		5	mils
5	DQS[x]-to-DQ[x] skew⁽⁶⁾⁽⁷⁾		25	mils
6	Center-to-center DQ[x] to other DDR3 trace spacing⁽⁸⁾⁽⁹⁾	4w
7	Center-to-center DQ[x] to other DQ[x] trace spacing⁽⁸⁾⁽¹⁰⁾	3w
8	DQS[x] center-to-center spacing⁽¹¹⁾
9	DQS[x] center-to-center spacing to other net⁽⁸⁾	4w

DQS[x] represents the DQS0 and DQS1 clock net classes, and DQ[x] represents the DQ0 and DQ1 signal net classes.
External termination disallowed. Data termination should use built-in ODT functionality.
DQLMn is the longest Manhattan distance of a byte. For definition, see Section 7.7.2.3.6.2 and Figure 7-67.
DQLM0 is the longest Manhattan length for the DQ0 net class.
DQLM1 is the longest Manhattan length for the DQ1 net class.
Length matching is only done within a byte. Length matching across bytes is not required.
Each DQS clock net class is length matched to its associated DQ signal net class.
Center-to-center spacing is allowed to fall to minimum for up to 1250 mils of routed length.
Other DDR3 trace spacing means signals that are not part of the same DQ[x] signal net class.
This applies to spacing within same DQ[x] signal net class.
DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Z_o x 2, where Z_o is the single-ended impedance defined in Table 7-62.