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ZHCS488K October 2011 – December 2018 AM3351 , AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

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机械数据 (封装 | 引脚)

ZCZ|324
ZCE|298

散热焊盘机械数据 (封装 | 引脚)

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Table 7-24 GPMC and NOR Flash Switching Characteristics—Synchronous Mode⁽²⁾

NO.	PARAMETER			OPP100		OPP50		UNIT
NO.	PARAMETER			MIN	MAX	MIN	MAX	UNIT
F0	1 / t_c(clk)	Frequency⁽¹⁸⁾, output clock gpmc_clk			100		50	MHz
F1	t_w(clkH)	Typical pulse duration, output clock gpmc_clk high		0.5P⁽¹⁵⁾	0.5P⁽¹⁵⁾	0.5P⁽¹⁵⁾	0.5P⁽¹⁵⁾	ns
F1	t_w(clkL)	Typical pulse duration, output clock gpmc_clk low		0.5P⁽¹⁵⁾	0.5P⁽¹⁵⁾	0.5P⁽¹⁵⁾	0.5P⁽¹⁵⁾	ns
	t_dc(clk)	Duty cycle error, output clock gpmc_clk		–500	500	–500	500	ps
	t_J(clk)	Jitter standard deviation⁽¹⁹⁾, output clock gpmc_clk			33.33		33.33	ps
F2	t_d(clkH-csnV)	Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x]⁽¹⁴⁾ transition		F⁽⁶⁾ - 2.2	F⁽⁶⁾ + 4.5	F⁽⁶⁾ - 3.2	F⁽⁶⁾ + 9.5	ns
F3	t_{d(clkH-csnIV)}	Delay time, output clock gpmc_clk rising edge to output chip select gpmc_csn[x]⁽¹⁴⁾ invalid		E⁽⁵⁾ – 2.2	E⁽⁵⁾ + 4.5	E⁽⁵⁾ – 3.2	E⁽⁵⁾ + 9.5	ns
F4	t_d(aV-clk)	Delay time, output address gpmc_a[27:1] valid to output clock gpmc_clk first edge		B⁽²⁾ – 4.5	B⁽²⁾ + 2.3	B⁽²⁾ – 5.5	B⁽²⁾ + 12.3	ns
F5	t_d(clkH-aIV)	Delay time, output clock gpmc_clk rising edge to output address gpmc_a[27:1] invalid		–2.3	4.5	–3.3	14.5	ns
F6	t_{d(be[x]nV-clk)}	Delay time, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n valid to output clock gpmc_clk first edge		B⁽²⁾ – 1.9	B⁽²⁾ + 2.3	B⁽²⁾ – 2.9	B⁽²⁾ + 12.3	ns
F7	t_{d(clkH-be[x]nIV)}	Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n invalid⁽¹¹⁾		D⁽⁴⁾ – 2.3	D⁽⁴⁾ + 1.9	D⁽⁴⁾ – 3.3	D⁽⁴⁾ + 6.9	ns
F7	t_{d(clkL-be[x]nIV)}	Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid⁽¹²⁾		D⁽⁴⁾ – 2.3	D⁽⁴⁾ + 1.9	D⁽⁴⁾ – 3.3	D⁽⁴⁾ + 6.9	ns
F7	t_{d(clkL-be[x]nIV)}	Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 invalid⁽¹³⁾		D⁽⁴⁾ – 2.3	D⁽⁴⁾ + 1.9	D⁽⁴⁾ – 3.3	D⁽⁴⁾ + 11.9	ns
F8	t_d(clkH-advn)	Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale transition		G⁽⁷⁾ – 2.3	G⁽⁷⁾ + 4.5	G⁽⁷⁾ – 3.3	G⁽⁷⁾ + 9.5	ns
F9	t_{d(clkH-advnIV)}	Delay time, output clock gpmc_clk rising edge to output address valid and address latch enable gpmc_advn_ale invalid		D⁽⁴⁾ – 2.3	D⁽⁴⁾ + 3.5	D⁽⁴⁾ – 3.3	D⁽⁴⁾ + 9.5	ns
F10	t_d(clkH-oen)	Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen transition		H⁽⁸⁾ – 2.3	H⁽⁸⁾ + 3.5	H⁽⁸⁾ – 3.3	H⁽⁸⁾ + 8.5	ns
F11	t_{d(clkH-oenIV)}	Delay time, output clock gpmc_clk rising edge to output enable gpmc_oen invalid		H⁽⁸⁾ – 2.3	H⁽⁸⁾ + 3.5	H⁽⁸⁾ – 3.3	H⁽⁸⁾ + 8.5	ns
F14	t_d(clkH-wen)	Delay time, output clock gpmc_clk rising edge to output write enable gpmc_wen transition		I⁽⁹⁾ – 2.3	I⁽⁹⁾ + 4.5	I⁽⁹⁾ – 3.3	I⁽⁹⁾ + 9.5	ns
F15	t_d(clkH-do)	Delay time, output clock gpmc_clk rising edge to output data gpmc_ad[15:0] transition⁽¹¹⁾		J⁽¹⁰⁾ – 2.3	J⁽¹⁰⁾ + 1.9	J⁽¹⁰⁾ – 3.3	J⁽¹⁰⁾ + 6.9	ns
F15	t_d(clkL-do)	Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition⁽¹²⁾		J⁽¹⁰⁾ – 2.3	J⁽¹⁰⁾ + 1.9	J⁽¹⁰⁾ – 3.3	J⁽¹⁰⁾ + 6.9	ns
F15	t_d(clkL-do)	Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition⁽¹³⁾		J⁽¹⁰⁾ – 2.3	J⁽¹⁰⁾ + 1.9	J⁽¹⁰⁾ – 3.3	J⁽¹⁰⁾ + 11.9	ns
F17	t_{d(clkH-be[x]n)}	Delay time, output clock gpmc_clk rising edge to output lower byte enable and command latch enable gpmc_be0n_cle transition⁽¹¹⁾		J⁽¹⁰⁾ – 2.3	J⁽¹⁰⁾ + 1.9	J⁽¹⁰⁾ – 3.3	J⁽¹⁰⁾ + 6.9	ns
F17	t_{d(clkL-be[x]n)}	Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition⁽¹²⁾		J⁽¹⁰⁾ – 2.3	J⁽¹⁰⁾ + 1.9	J⁽¹⁰⁾ – 3.3	J⁽¹⁰⁾ + 6.9	ns
F17	t_{d(clkL-be[x]n)}	Delay time, gpmc_clk falling edge to gpmc_nbe0_cle, gpmc_nbe1 transition⁽¹³⁾		J⁽¹⁰⁾ – 2.3	J⁽¹⁰⁾ + 1.9	J⁽¹⁰⁾ – 3.3	J⁽¹⁰⁾ + 11.9	ns
F18	t_w(csnV)	Pulse duration, output chip select gpmc_csn[x]⁽¹⁴⁾ low	Read	A⁽¹⁾		A⁽¹⁾		ns
F18	t_w(csnV)	Pulse duration, output chip select gpmc_csn[x]⁽¹⁴⁾ low	Write	A⁽¹⁾		A⁽¹⁾		ns
F19	t_w(be[x]nV)	Pulse duration, output lower byte enable and command latch enable gpmc_be0n_cle, output upper byte enable gpmc_be1n low	Read	C⁽³⁾		C⁽³⁾		ns
F19	t_w(be[x]nV)		Write	C⁽³⁾		C⁽³⁾		ns
F20	t_w(advnV)	Pulse duration, output address valid and address latch enable gpmc_advn_ale low	Read	K⁽¹⁶⁾		K⁽¹⁶⁾		ns
F20	t_w(advnV)		Write	K⁽¹⁶⁾		K⁽¹⁶⁾		ns

For single read: A = (CSRdOffTime – CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
With n being the page burst access number.
B = ClkActivationTime × GPMC_FCLK⁽¹⁷⁾
For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK ⁽¹⁷⁾
For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
With n being the page burst access number.
For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For csn falling edge (CS activated):
- Case GpmcFCLKDivider = 0:
  - F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
  - F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - F = 0.5 × CSExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((CSOnTime – ClkActivationTime) is a multiple of 3)
  - F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
  - F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV falling edge (ADV activated):
- Case GpmcFCLKDivider = 0:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
  - G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
  - G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
  - G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
- Case GpmcFCLKDivider = 0:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
  - G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
  - G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
  - G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
- Case GpmcFCLKDivider = 0:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
  - G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - G = 0.5 × ADVExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
  - G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
  - G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
For OE falling edge (OE activated) and I/O DIR rising edge (Data Bus input direction):
- Case GpmcFCLKDivider = 0:
  - H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
  - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((OEOnTime – ClkActivationTime) is a multiple of 3)
  - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
  - H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
- Case GpmcFCLKDivider = 0:
  - H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
  - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - H = 0.5 × OEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((OEOffTime – ClkActivationTime) is a multiple of 3)
  - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
  - H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
For WE falling edge (WE activated):
- Case GpmcFCLKDivider = 0:
  - I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
  - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((WEOnTime – ClkActivationTime) is a multiple of 3)
  - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
  - I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
- Case GpmcFCLKDivider = 0:
  - I = 0.5 × WEExtraDelay × GPMC_FCLK ⁽¹⁷⁾
- Case GpmcFCLKDivider = 1:
  - I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
  - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ otherwise
- Case GpmcFCLKDivider = 2:
  - I = 0.5 × WEExtraDelay × GPMC_FCLK⁽¹⁷⁾ if ((WEOffTime – ClkActivationTime) is a multiple of 3)
  - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
  - I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK⁽¹⁷⁾ if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
J = GPMC_FCLK⁽¹⁷⁾
First transfer only for CLK DIV 1 mode.
Half cycle; for all data after initial transfer for CLK DIV 1 mode.
Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5. In gpmc_wait[x], x is equal to 0 or 1.
P = gpmc_clk period in ns
For read: K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁷⁾
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
The jitter probability density can be approximated by a Gaussian function.