米6体育平台手机版

ZHCSDC3D June 2014 – September 2016 AM4372 , AM4376 , AM4377 , AM4378 , AM4379

PRODUCTION DATA.

请参考 PDF 数据表获取器件具体的封装图。

NO.			OPP100		OPP50		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
FA5⁽¹⁾	t_acc(d)	Data access time		H⁽⁴⁾		H⁽⁴⁾	ns
FA20⁽²⁾	t_{acc1-pgmode(d)}	Page mode successive data access time		P⁽⁵⁾		P⁽⁵⁾	ns
FA21⁽³⁾	t_{acc2-pgmode(d)}	Page mode first data access time		H⁽⁴⁾		H⁽⁴⁾	ns

The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾
P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾
GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.