5.10.3 Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the Section 4.2, Pin Attributes of the Section 4, Terminal Configuration and Functions to determine which power supplies are applicable.

Figure 5-5 and Figure 5-6, describe the device Power Sequencing.

Figure 5-5 Power-Up Sequencing

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. vdd must ramp before or at the same time as vdd_dsp.
4. If any of the vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
5. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.
6. vdds and vdda rails must not be combined together.
7. porz must remain asserted low until all of the following conditions are met:
   • All device supply rails reach stable operational levels.
   • xi_osc0 is stable and at a valid frequency.
   • Minimum of 12P after both of the above conditions are met, where P = 1 / (SYS_CLK1/610), units in ns.
     resetn must be high prior to, or rise simultaneous with, porz but not before its power supply, vddshv3, rising.
8. Setup time: sysboot[15:0] pins must be valid 2P⁽¹¹⁾ before porz is de-asserted high.
9. Hold time: sysboot[15:0] pins must be valid 15P⁽¹¹⁾ after porz is de-asserted high.
10. rstoutn will be asserted low when porz is low, and de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.
11. P = 1/(SYS_CLK1/610) frequency in ns.
12. ddr1_vref0 may rise coincident with vdds_ddr1 or at a later time. However, it must be valid before porz rising.
13. vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_usb3 can be energized concurrently or after vdda33v_usb1, vdda33v_usb2.

Figure 5-6 Power-Down Sequencing⁽⁸⁾⁽⁹⁾

1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
3. xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.
4. vdd must ramp after or at the same time as vdd_dsp.
5. If any of the vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
   • vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode.
   • If vddshv1, vddshv3, vddshv4, vddshv7, vddshv[9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshv[1, 3-4, 7, 9-11] rail is never higher than 2.0 V above the vdds18v rail.
6. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.
7. The 1.8V vdda_* supplies can either ramp down at the earlier time period shown or can be delayed to ramp down after the core supplies coincident with the vdds18v supply as long as porz is asserted (low) during the power down sequence.
8. The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC that is recommended for use with this SoC. The accelerated sequence has porz go low first followed immediately by 3.3V vddshvx supplies and vddshv8 simultaneously second, 1.8V PHY, 3.3V USB and core supplies simultaneously third, DDR supplies, DDR references and 1.8V PLL supplies simultaneously fourth and all other 1.8V supplies simultaneously last.
9. Ramped Down is defined as reaching a voltage level of no more than 0.6V.
10. ddr1_vref0 may fall coincident with vdds_ddr1, or at a prior time but after porz is asserted low.

Figure 5-7 describes vddshv[1, 3-4, 7, 9-11] Supplies Falling Before vdds18v Supplies Delta.

Figure 5-7 vddshv* Supplies Falling After vdds18v Supplies Delta

1. Vdelta MAX = 2V
2. If vddshv8 is powered by the same supply source as the other vddshv[1, 3-4, 7, 9-11] rails.