ZHCSF38G March   2016  – May 2018 AM5716 , AM5718

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Device Comparison Table
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
        3. 6.1.4.3 RC On-die Oscillator Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-33 Timing Requirements for I2C Input Timings
      2. Table 7-34 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-35 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-40 Timing Requirements for UART
      2. Table 7-41 Switching Characteristics Over Recommended Operating Conditions for UART
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
      1. Table 7-48 Timing Requirements for McASP1
      2. Table 7-49 Timing Requirements for McASP2
      3. Table 7-50 Timing Requirements for McASP3/4/5/6/7/8
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.23.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High-speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High-speed JC64 DDR, 8-bit data
          1. Table 7-110 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-132 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-133 PRU-ICSS PRU Switching Requirements - Direct Output Mode
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-134 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-135 PRU-ICSS PRU Timing Requirements - Shift In Mode
          2. Table 7-136 PRU-ICSS PRU Switching Requirements - Shift Out Mode
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
          1. Table 7-137 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
          2. Table 7-138 PRU-ICSS PRU Timing Requirements - EnDAT Mode
          3. Table 7-139 PRU-ICSS PRU Switching Requirements - EnDAT Mode
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-140 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
          2. Table 7-141 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
          3. Table 7-142 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
          4. Table 7-143 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-144 PRU-ICSS ECAT Switching Requirements - Digital IOs
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-145 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
          2. Table 7-146 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-147 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-148 PRU-ICSS MII_RT Timing Requirements - MII[x]_RXCLK
          2. Table 7-149 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-150 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-151 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-152 Timing Requirements for PRU-ICSS UART Receive
        2. Table 7-153 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-173 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-174 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-175 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-176 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Thermal Solution Guidance
    6. 8.6 Single-Ended Interfaces
      1. 8.6.1 General Routing Guidelines
      2. 8.6.2 QSPI Board Design and Layout Guidelines
    7. 8.7 LJCB_REFN/P Connections
    8. 8.8 Clock Routing Guidelines
      1. 8.8.1 32-kHz Oscillator Routing
      2. 8.8.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Related Links
    6. 9.6 Community Resources
    7. 9.7 Trademarks
    8. 9.8 静电放电警告
    9. 9.9 术语表
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.4 Recommended Operating Conditions

The device is used under the recommended operating conditions described in Table 5-5.

NOTE

Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.

Table 5-5 Recommended Operating Conditions

PARAMETER DESCRIPTION MIN (2) NOM MAX DC (3) MAX (2) UNIT
Input Power Supply Voltage Range
vdd Core voltage domain supply See Section 5.5 V
vdd_mpu Supply voltage range for MPU domain See Section 5.5 V
vdd_gpu GPU voltage domain supply See Section 5.5 V
vdd_dsp DSP voltage domain supply See Section 5.5 V
vdd_iva IVA voltage domain supply See Section 5.5 V
vdd_rtc RTC voltage domain supply See Section 5.5 V
vdda_usb1 DPLL_USB and HS USB1 1.8V analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_usb2 HS USB2 1.8V analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda33v_usb1 HS USB1 3.3V analog power supply.If USB1 is not used, this pin can alternatively be connected to VSS if the following requirements are met:
- The usb1_dm/usb1_dp pins are left unconnected
- The USB1 PHY is kept powered down 		3.135 3.3 3.366 3.465 V
Maximum noise (peak-peak) 50 mVPPmax
vdda33v_usb2 HS USB2 3.3V analog power supply. If USB2 is not used, this pin can alternatively be connected to VSS if the following requirements are met:
- The usb2_dm/usb2_dp pins are left unconnected
- The USB2 PHY is kept powered down 		3.135 3.3 3.366 3.465 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_per PER PLL and PER HSDIVIDER analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_ddr DPLL_DDR and DDR HSDIVIDER analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_debug DPLL_DEBUG analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_dsp_iva DPLL_DSP and DPLL_IVA analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_core_gmac DPLL_CORE and CORE HSDIVIDER analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_pll_spare DPLL_SPARE analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_gpu DPLL_GPU analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_hdmi PLL_HDMI and HDMI analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_pcie DPLL_PCIe_REF and PCIe analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_pcie0 PCIe ch0 RX/TX analog power supply 1.71 1.80 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_sata DPLL_SATA and SATA RX/TX analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_usb3 DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_video DPLL_VIDEO1 analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdds_mlbp MLBP IO power supply 1.71 1.80 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_mpu_abe DPLL_MPU analog power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_osc HFOSC analog power supply 1.71 1.80 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_rtc RTC bias and RTC LFOSC analog power supply 1.71 1.80 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdda_csi CSI Interface 1.8v Supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdds18v 1.8V power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdds18v_ddr1 EMIF1 bias power supply 1.71 1.80 1.836 1.89 V
Maximum noise (peak-peak) 50 mVPPmax
vdds_ddr1 EMIF1 power supply (1.5V for DDR3 mode / 1.35V DDR3L mode) 1.35-V Mode 1.28 1.35 1.377 1.42 V
1.5-V Mode 1.43 1.50 1.53 1.57
Maximum noise (peak-peak) 1.35-V Mode 50 mVPPmax
1.5-V Mode
vddshv5 Dual Voltage (1.8V or 3.3V) power supply for the RTC Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv1 Dual Voltage (1.8V or 3.3V) power supply for the VIN2 Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv10 Dual Voltage (1.8V or 3.3V) power supply for the GPMC Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv11 Dual Voltage (1.8V or 3.3V) power supply for the MMC2 Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv2 Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv3 Dual Voltage (1.8V or 3.3V) power supply for the GENERAL Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv4 Dual Voltage (1.8V or 3.3V) power supply for the MMC4 Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv6 Dual Voltage (1.8V or 3.3V) power supply for the VIN1 Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv7 Dual Voltage (1.8V or 3.3V) power supply for the WIFI Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv8 Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vddshv9 Dual Voltage (1.8V or 3.3V) power supply for the RGMII Power Group pins 1.8-V Mode 1.71 1.80 1.836 1.89 V
3.3-V Mode 3.135 3.30 3.366 3.465
Maximum noise (peak-peak) 1.8-V Mode 50 mVPPmax
3.3-V Mode
vss Ground supply 0 V
vssa_hdmi DPLL_HDMI and HDMI PHY analog ground 0 V
vssa_pcie PCIe analog ground 0 V
vssa_usb HS USB1 and HS USB2 analog ground 0 V
vssa_usb3 DPLL_USB and USB3.0 RX/TX analog ground 0 V
vssa_csi CSI Interface 0v Supply 0 V
vssa_sata SATA TX ground 0 V
vssa_video DPLL_VIDEO1 analog ground 0 V
vssa_osc0 OSC0 analog ground 0 V
vssa_osc1 OSC1 analog ground 0 V
TJ(1) Operating junction temperature range Commercial 0 90 °C
Extended -40 105
Automotive -40 125
ddr1_vref0 Reference Power Supply EMIF1 0.5*vdds_ddr1 V
  1. Refer to Power on Hours table for limitations.
  2. The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
  3. The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH (Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
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