ZHCSG49F December   2015  – May 2019 AM5726 , AM5728 , AM5729

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Port (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface - (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timer
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9  Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10 Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11 Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12 Multichannel Audio Serial Port (McASP)
      13. 4.4.13 Universal Serial Bus (USB)
      14. 4.4.14 Serial Advanced Technology Attachment (SATA)
      15. 4.4.15 Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16 Controller Area Network Interface (DCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 Media Local Bus (MLB) Interface
      19. 4.4.19 eMMC/SD/SDIO
      20. 4.4.20 General-Purpose Interface (GPIO)
      21. 4.4.21 Keyboard controller (KBD)
      22. 4.4.22 Pulse Width Modulation (PWM)
      23. 4.4.23 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      24. 4.4.24 Test Interfaces
      25. 4.4.25 System and Miscellaneous
        1. 4.4.25.1 Sysboot
        2. 4.4.25.2 Power, Reset and Clock Management (PRCM)
        3. 4.4.25.3 Real-Time Clock (RTC) Interface
        4. 4.4.25.4 System Direct Memory Access (SDMA)
        5. 4.4.25.5 Interrupt Controllers (INTC)
        6. 4.4.25.6 Observability
        7. 4.4.25.7 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  BC1833IHHV Buffers DC Electrical Characteristics
      8. 5.7.8  USBPHY DC Electrical Characteristics
      9. 5.7.9  Dual Voltage SDIO1833 DC Electrical Characteristics
      10. 5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics
      11. 5.7.11 SATAPHY DC Electrical Characteristics
      12. 5.7.12 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1 HDQ / 1-Wire — HDQ Mode
      2. 7.13.2 HDQ/1-Wire—1-Wire Mode
    14. 7.14 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-41 Timing Requirements for UART
      2. Table 7-42 Switching Characteristics Over Recommended Operating Conditions for UART
    15. 7.15 Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16 Quad Serial Peripheral Interface (QSPI)
    17. 7.17 Multichannel Audio Serial Port (McASP)
      1. Table 7-49 Timing Requirements for McASP1
      2. Table 7-50 Timing Requirements for McASP2
      3. Table 7-51 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-52 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-53 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    18. 7.18 Universal Serial Bus (USB)
      1. 7.18.1 USB1 DRD PHY
      2. 7.18.2 USB2 PHY
    19. 7.19 Serial Advanced Technology Attachment (SATA)
    20. 7.20 Peripheral Component Interconnect Express (PCIe)
    21. 7.21 Controller Area Network Interface (DCAN)
    22. 7.22 Ethernet Interface (GMAC_SW)
      1. 7.22.1 GMAC MII Timings
        1. Table 7-68 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-69 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-70 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-71 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.22.2 GMAC MDIO Interface Timings
      3. 7.22.3 GMAC RMII Timings
        1. Table 7-76 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-77 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-79 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.22.4 GMAC RGMII Timings
        1. Table 7-83 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-84 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-85 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-86 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    23. 7.23 eMMC/SD/SDIO
      1. 7.23.1 MMC1—SD Card Interface
        1. 7.23.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.23.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.23.1.3 SDR12, 4-bit data, half-cycle
        4. 7.23.1.4 SDR25, 4-bit data, half-cycle
        5. 7.23.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.23.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.23.1.7 UHS-I DDR50, 4-bit data
      2. 7.23.2 MMC2 — eMMC
        1. 7.23.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.23.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.23.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.23.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.23.3 MMC3 and MMC4—SDIO/SD
        1. 7.23.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.23.3.2 MMC3 and MMC4, SD High Speed
        3. 7.23.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.23.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.23.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    24. 7.24 General-Purpose Interface (GPIO)
    25. 7.25 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.25.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.25.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-135 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-136 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        2. 7.25.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-137 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        3. 7.25.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-138 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-139 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.25.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.25.2.1 PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-140 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-141 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-142 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-143 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-144 PRU-ICSS ECAT Switching Requirements - Digital IOs
      3. 7.25.3 PRU-ICSS MII_RT and Switch
        1. 7.25.3.1 PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-145 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-146 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-147 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        2. 7.25.3.2 PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-148 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
          2. Table 7-149 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-150 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-151 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.25.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-152 Timing Requirements for PRU-ICSS UART Receive
        2. Table 7-153 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      5. 7.25.5 PRU-ICSS IOSETs
      6. 7.25.6 PRU-ICSS Manual Functional Mapping
    26. 7.26 System and Miscellaneous interfaces
    27. 7.27 Test Interfaces
      1. 7.27.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.27.1.1 JTAG Electrical Data/Timing
          1. Table 7-174 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-175 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-176 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-177 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.27.2 Trace Port Interface Unit (TPIU)
        1. 7.27.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIFs
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Thermal Solution Guidance
    6. 8.6 Single-Ended Interfaces
      1. 8.6.1 General Routing Guidelines
      2. 8.6.2 QSPI Board Design and Layout Guidelines
    7. 8.7 LJCB_REFN/P Connections
    8. 8.8 Clock Routing Guidelines
      1. 8.8.1 32-kHz Oscillator Routing
      2. 8.8.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商标
    7. 9.7 静电放电警告
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

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7.25.6 PRU-ICSS Manual Functional Mapping

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU0 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-156Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Output mode for a definition of the Manual modes.

Table 7-156 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-156 Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Output mode

BALL BALL NAME PR1_PRU0_DIR_OUT_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
AG3 vin1a_d10 0 600 CFG_VIN1A_D10_OUT pr1_pru0_gpo7
AG5 vin1a_d11 0 0 CFG_VIN1A_D11_OUT pr1_pru0_gpo8
AF2 vin1a_d12 0 2700 CFG_VIN1A_D12_OUT pr1_pru0_gpo9
AF6 vin1a_d13 0 200 CFG_VIN1A_D13_OUT pr1_pru0_gpo10
AF3 vin1a_d14 0 800 CFG_VIN1A_D14_OUT pr1_pru0_gpo11
AF4 vin1a_d15 0 0 CFG_VIN1A_D15_OUT pr1_pru0_gpo12
AF1 vin1a_d16 0 100 CFG_VIN1A_D16_OUT pr1_pru0_gpo13
AE3 vin1a_d17 0 300 CFG_VIN1A_D17_OUT pr1_pru0_gpo14
AE5 vin1a_d18 0 0 CFG_VIN1A_D18_OUT pr1_pru0_gpo15
AE1 vin1a_d19 0 400 CFG_VIN1A_D19_OUT pr1_pru0_gpo16
AE2 vin1a_d20 0 300 CFG_VIN1A_D20_OUT pr1_pru0_gpo17
AE6 vin1a_d21 0 500 CFG_VIN1A_D21_OUT pr1_pru0_gpo18
AD2 vin1a_d22 0 0 CFG_VIN1A_D22_OUT pr1_pru0_gpo19
AD3 vin1a_d23 0 500 CFG_VIN1A_D23_OUT pr1_pru0_gpo20
AH6 vin1a_d3 0 1600 CFG_VIN1A_D3_OUT pr1_pru0_gpo0
AH3 vin1a_d4 0 2800 CFG_VIN1A_D4_OUT pr1_pru0_gpo1
AH5 vin1a_d5 0 0 CFG_VIN1A_D5_OUT pr1_pru0_gpo2
AG6 vin1a_d6 0 0 CFG_VIN1A_D6_OUT pr1_pru0_gpo3
AH4 vin1a_d7 0 0 CFG_VIN1A_D7_OUT pr1_pru0_gpo4
AG4 vin1a_d8 0 0 CFG_VIN1A_D8_OUT pr1_pru0_gpo5
AG2 vin1a_d9 0 0 CFG_VIN1A_D9_OUT pr1_pru0_gpo6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-157Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the Manual modes.

Table 7-157 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-157 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode

BALL BALL NAME PR1_PRU1_DIR_OUT_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
D3 vin2a_d10 0 1900 CFG_VIN2A_D10_OUT pr1_pru1_gpo7
F6 vin2a_d11 0 2700 CFG_VIN2A_D11_OUT pr1_pru1_gpo8
D5 vin2a_d12 0 3400 CFG_VIN2A_D12_OUT pr1_pru1_gpo9
C2 vin2a_d13 0 3200 CFG_VIN2A_D13_OUT pr1_pru1_gpo10
C3 vin2a_d14 0 3000 CFG_VIN2A_D14_OUT pr1_pru1_gpo11
C4 vin2a_d15 0 2900 CFG_VIN2A_D15_OUT pr1_pru1_gpo12
B2 vin2a_d16 0 2700 CFG_VIN2A_D16_OUT pr1_pru1_gpo13
D6 vin2a_d17 0 3000 CFG_VIN2A_D17_OUT pr1_pru1_gpo14
C5 vin2a_d18 0 2200 CFG_VIN2A_D18_OUT pr1_pru1_gpo15
A3 vin2a_d19 0 2300 CFG_VIN2A_D19_OUT pr1_pru1_gpo16
B3 vin2a_d20 0 1800 CFG_VIN2A_D20_OUT pr1_pru1_gpo17
B4 vin2a_d21 0 1900 CFG_VIN2A_D21_OUT pr1_pru1_gpo18
B5 vin2a_d22 0 1400 CFG_VIN2A_D22_OUT pr1_pru1_gpo19
A4 vin2a_d23 0 1900 CFG_VIN2A_D23_OUT pr1_pru1_gpo20
E2 vin2a_d3 0 3900 CFG_VIN2A_D3_OUT pr1_pru1_gpo0
D2 vin2a_d4 0 5100 CFG_VIN2A_D4_OUT pr1_pru1_gpo1
F4 vin2a_d5 0 0 CFG_VIN2A_D5_OUT pr1_pru1_gpo2
C1 vin2a_d6 0 2700 CFG_VIN2A_D6_OUT pr1_pru1_gpo3
E4 vin2a_d7 0 2600 CFG_VIN2A_D7_OUT pr1_pru1_gpo4
F5 vin2a_d8 0 2500 CFG_VIN2A_D8_OUT pr1_pru1_gpo5
E6 vin2a_d9 0 1900 CFG_VIN2A_D9_OUT pr1_pru1_gpo6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU0 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-158Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Input mode for a definition of the Manual modes.

Table 7-158 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-158 Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Input mode

BALL BALL NAME PR1_PRU0_DIR_IN_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
AG3 vin1a_d10 0 0 CFG_VIN1A_D10_IN pr1_pru0_gpi7
AG5 vin1a_d11 0 300 CFG_VIN1A_D11_IN pr1_pru0_gpi8
AF2 vin1a_d12 0 800 CFG_VIN1A_D12_IN pr1_pru0_gpi9
AF6 vin1a_d13 0 0 CFG_VIN1A_D13_IN pr1_pru0_gpi10
AF3 vin1a_d14 0 600 CFG_VIN1A_D14_IN pr1_pru0_gpi11
AF4 vin1a_d15 0 1100 CFG_VIN1A_D15_IN pr1_pru0_gpi12
AF1 vin1a_d16 0 800 CFG_VIN1A_D16_IN pr1_pru0_gpi13
AE3 vin1a_d17 0 1000 CFG_VIN1A_D17_IN pr1_pru0_gpi14
AE5 vin1a_d18 0 1100 CFG_VIN1A_D18_IN pr1_pru0_gpi15
AE1 vin1a_d19 0 2800 CFG_VIN1A_D19_IN pr1_pru0_gpi16
AE2 vin1a_d20 0 900 CFG_VIN1A_D20_IN pr1_pru0_gpi17
AE6 vin1a_d21 0 800 CFG_VIN1A_D21_IN pr1_pru0_gpi18
AD2 vin1a_d22 0 1400 CFG_VIN1A_D22_IN pr1_pru0_gpi19
AD3 vin1a_d23 0 1001 CFG_VIN1A_D23_IN pr1_pru0_gpi20
AH6 vin1a_d3 0 600 CFG_VIN1A_D3_IN pr1_pru0_gpi0
AH3 vin1a_d4 0 0 CFG_VIN1A_D4_IN pr1_pru0_gpi1
AH5 vin1a_d5 0 900 CFG_VIN1A_D5_IN pr1_pru0_gpi2
AG6 vin1a_d6 0 400 CFG_VIN1A_D6_IN pr1_pru0_gpi3
AH4 vin1a_d7 0 500 CFG_VIN1A_D7_IN pr1_pru0_gpi4
AG4 vin1a_d8 0 0 CFG_VIN1A_D8_IN pr1_pru0_gpi5
AG2 vin1a_d9 0 0 CFG_VIN1A_D9_IN pr1_pru0_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-159Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the Manual modes.

Table 7-159 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-159 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode

BALL BALL NAME PR1_PRU1_DIR_IN_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D3 vin2a_d10 0 1600 CFG_VIN2A_D10_IN pr1_pru1_gpi7
F6 vin2a_d11 0 1000 CFG_VIN2A_D11_IN pr1_pru1_gpi8
D5 vin2a_d12 0 1400 CFG_VIN2A_D12_IN pr1_pru1_gpi9
C2 vin2a_d13 0 800 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C3 vin2a_d14 0 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
C4 vin2a_d15 0 1600 CFG_VIN2A_D15_IN pr1_pru1_gpi12
B2 vin2a_d16 0 1200 CFG_VIN2A_D16_IN pr1_pru1_gpi13
D6 vin2a_d17 0 1500 CFG_VIN2A_D17_IN pr1_pru1_gpi14
C5 vin2a_d18 0 1000 CFG_VIN2A_D18_IN pr1_pru1_gpi15
A3 vin2a_d19 0 1100 CFG_VIN2A_D19_IN pr1_pru1_gpi16
B3 vin2a_d20 0 700 CFG_VIN2A_D20_IN pr1_pru1_gpi17
B4 vin2a_d21 0 1300 CFG_VIN2A_D21_IN pr1_pru1_gpi18
B5 vin2a_d22 0 1400 CFG_VIN2A_D22_IN pr1_pru1_gpi19
A4 vin2a_d23 0 1300 CFG_VIN2A_D23_IN pr1_pru1_gpi20
E2 vin2a_d3 0 2100 CFG_VIN2A_D3_IN pr1_pru1_gpi0
D2 vin2a_d4 0 1000 CFG_VIN2A_D4_IN pr1_pru1_gpi1
F4 vin2a_d5 0 1700 CFG_VIN2A_D5_IN pr1_pru1_gpi2
C1 vin2a_d6 0 700 CFG_VIN2A_D6_IN pr1_pru1_gpi3
E4 vin2a_d7 0 1300 CFG_VIN2A_D7_IN pr1_pru1_gpi4
F5 vin2a_d8 0 1700 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E6 vin2a_d9 0 1600 CFG_VIN2A_D9_IN pr1_pru1_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU0 Parallel Capture mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-160Manual Functions Mapping for PRU-ICSS1 PRU0 Parallel Capture mode for a definition of the Manual modes.

Table 7-160 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-160 Manual Functions Mapping for PRU-ICSS1 PRU0 Parallel Capture mode

BALL BALL NAME PR1_PRU0_PAR_CAP_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
AG3 vin1a_d10 637 0 CFG_VIN1A_D10_IN pr1_pru0_gpi7
AG5 vin1a_d11 419 0 CFG_VIN1A_D11_IN pr1_pru0_gpi8
AF2 vin1a_d12 714 0 CFG_VIN1A_D12_IN pr1_pru0_gpi9
AF6 vin1a_d13 405 0 CFG_VIN1A_D13_IN pr1_pru0_gpi10
AF3 vin1a_d14 761 0 CFG_VIN1A_D14_IN pr1_pru0_gpi11
AF4 vin1a_d15 714 0 CFG_VIN1A_D15_IN pr1_pru0_gpi12
AF1 vin1a_d16 608 0 CFG_VIN1A_D16_IN pr1_pru0_gpi13
AE3 vin1a_d17 733 0 CFG_VIN1A_D17_IN pr1_pru0_gpi14
AE5 vin1a_d18 743 0 CFG_VIN1A_D18_IN pr1_pru0_gpi15
AE1 vin1a_d19 0 166 CFG_VIN1A_D19_IN pr1_pru0_gpi16
AH6 vin1a_d3 435 0 CFG_VIN1A_D3_IN pr1_pru0_gpi0
AH3 vin1a_d4 449 0 CFG_VIN1A_D4_IN pr1_pru0_gpi1
AH5 vin1a_d5 501 0 CFG_VIN1A_D5_IN pr1_pru0_gpi2
AG6 vin1a_d6 362 0 CFG_VIN1A_D6_IN pr1_pru0_gpi3
AH4 vin1a_d7 382 0 CFG_VIN1A_D7_IN pr1_pru0_gpi4
AG4 vin1a_d8 488 0 CFG_VIN1A_D8_IN pr1_pru0_gpi5
AG2 vin1a_d9 649 0 CFG_VIN1A_D9_IN pr1_pru0_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS1 PRU1 Parallel Capture mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-161Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture mode for a definition of the Manual modes.

Table 7-161 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-161 Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture mode

BALL BALL NAME PR1_PRU1_PAR_CAP_MANUAL CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D3 vin2a_d10 2693 441 CFG_VIN2A_D10_IN pr1_pru1_gpi7
F6 vin2a_d11 2580 0 CFG_VIN2A_D11_IN pr1_pru1_gpi8
D5 vin2a_d12 2531 348 CFG_VIN2A_D12_IN pr1_pru1_gpi9
C2 vin2a_d13 2409 0 CFG_VIN2A_D13_IN pr1_pru1_gpi10
C3 vin2a_d14 1792 0 CFG_VIN2A_D14_IN pr1_pru1_gpi11
C4 vin2a_d15 2644 121 CFG_VIN2A_D15_IN pr1_pru1_gpi12
B2 vin2a_d16 2478 146 CFG_VIN2A_D16_IN pr1_pru1_gpi13
D6 vin2a_d17 2542 350 CFG_VIN2A_D17_IN pr1_pru1_gpi14
C5 vin2a_d18 2728 64 CFG_VIN2A_D18_IN pr1_pru1_gpi15
A3 vin2a_d19 0 0 CFG_VIN2A_D19_IN pr1_pru1_gpi16
E2 vin2a_d3 2908 562 CFG_VIN2A_D3_IN pr1_pru1_gpi0
D2 vin2a_d4 2684 0 CFG_VIN2A_D4_IN pr1_pru1_gpi1
F4 vin2a_d5 2904 234 CFG_VIN2A_D5_IN pr1_pru1_gpi2
C1 vin2a_d6 2488 0 CFG_VIN2A_D6_IN pr1_pru1_gpi3
E4 vin2a_d7 2600 124 CFG_VIN2A_D7_IN pr1_pru1_gpi4
F5 vin2a_d8 2590 547 CFG_VIN2A_D8_IN pr1_pru1_gpi5
E6 vin2a_d9 2690 248 CFG_VIN2A_D9_IN pr1_pru1_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-162Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode for a definition of the Manual modes.

Table 7-162 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-162 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode

BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D7 vout1_d10 0 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7
D8 vout1_d11 0 756 CFG_VOUT1_D11_IN pr2_pru0_gpi8
A5 vout1_d12 0 531 CFG_VOUT1_D12_IN pr2_pru0_gpi9
C6 vout1_d13 0 180 CFG_VOUT1_D13_IN pr2_pru0_gpi10
C8 vout1_d14 0 334 CFG_VOUT1_D14_IN pr2_pru0_gpi11
C7 vout1_d15 0 1361 CFG_VOUT1_D15_IN pr2_pru0_gpi12
B7 vout1_d16 0 488 CFG_VOUT1_D16_IN pr2_pru0_gpi13
B8 vout1_d17 0 321 CFG_VOUT1_D17_IN pr2_pru0_gpi14
A7 vout1_d18 0 254 CFG_VOUT1_D18_IN pr2_pru0_gpi15
A8 vout1_d19 0 500 CFG_VOUT1_D19_IN pr2_pru0_gpi16
C9 vout1_d20 0 716 CFG_VOUT1_D20_IN pr2_pru0_gpi17
A9 vout1_d21 0 0 CFG_VOUT1_D21_IN pr2_pru0_gpi18
B9 vout1_d22 0 404 CFG_VOUT1_D22_IN pr2_pru0_gpi19
A10 vout1_d23 0 290 CFG_VOUT1_D23_IN pr2_pru0_gpi20
G11 vout1_d3 0 226 CFG_VOUT1_D3_IN pr2_pru0_gpi0
E9 vout1_d4 0 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1
F9 vout1_d5 0 365 CFG_VOUT1_D5_IN pr2_pru0_gpi2
F8 vout1_d6 0 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3
E7 vout1_d7 0 218 CFG_VOUT1_D7_IN pr2_pru0_gpi4
E8 vout1_d8 0 186 CFG_VOUT1_D8_IN pr2_pru0_gpi5
D9 vout1_d9 0 308 CFG_VOUT1_D9_IN pr2_pru0_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-163Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a definition of the Manual modes.

Table 7-163 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-163 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode

BALL BALL NAME PR2_PRU0_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
AC5 gpio6_10 1000 3900 CFG_GPIO6_10_IN pr2_pru0_gpi0
AB4 gpio6_11 1000 4500 CFG_GPIO6_11_IN pr2_pru0_gpi1
F14 mcasp1_axr15 0 1800 CFG_MCASP1_AXR15_IN pr2_pru0_gpi20
A19 mcasp2_aclkx 0 700 CFG_MCASP2_ACLKX_IN pr2_pru0_gpi18
C15 mcasp2_axr2 0 1700 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
A16 mcasp2_axr3 0 1800 CFG_MCASP2_AXR3_IN pr2_pru0_gpi17
A18 mcasp2_fsx 0 1100 CFG_MCASP2_FSX_IN pr2_pru0_gpi19
B19 mcasp3_axr0 0 1100 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
C17 mcasp3_axr1 0 1200 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
F15 mcasp3_fsx 0 1400 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
AD4 mmc3_clk 1000 4500 CFG_MMC3_CLK_IN pr2_pru0_gpi2
AC4 mmc3_cmd 1000 4000 CFG_MMC3_CMD_IN pr2_pru0_gpi3
AC7 mmc3_dat0 1000 4200 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AC6 mmc3_dat1 1000 3800 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AC9 mmc3_dat2 1000 3800 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
AC3 mmc3_dat3 1000 4400 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
AC8 mmc3_dat4 1000 4100 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AD6 mmc3_dat5 1000 4000 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AB8 mmc3_dat6 1000 3900 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB5 mmc3_dat7 1000 3500 CFG_MMC3_DAT7_IN pr2_pru0_gpi11
B18 mcasp3_aclkx 0 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-164Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode for a definition of the Manual modes.

Table 7-164 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-164 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode

BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
D7 vout1_d10 0 0 CFG_VOUT1_D10_OUT pr2_pru0_gpo7
D8 vout1_d11 0 200 CFG_VOUT1_D11_OUT pr2_pru0_gpo8
A5 vout1_d12 0 2300 CFG_VOUT1_D12_OUT pr2_pru0_gpo9
C6 vout1_d13 0 450 CFG_VOUT1_D13_OUT pr2_pru0_gpo10
C8 vout1_d14 0 600 CFG_VOUT1_D14_OUT pr2_pru0_gpo11
C7 vout1_d15 0 500 CFG_VOUT1_D15_OUT pr2_pru0_gpo12
B7 vout1_d16 0 100 CFG_VOUT1_D16_OUT pr2_pru0_gpo13
B8 vout1_d17 0 300 CFG_VOUT1_D17_OUT pr2_pru0_gpo14
A7 vout1_d18 0 700 CFG_VOUT1_D18_OUT pr2_pru0_gpo15
A8 vout1_d19 0 700 CFG_VOUT1_D19_OUT pr2_pru0_gpo16
C9 vout1_d20 0 900 CFG_VOUT1_D20_OUT pr2_pru0_gpo17
A9 vout1_d21 0 900 CFG_VOUT1_D21_OUT pr2_pru0_gpo18
B9 vout1_d22 0 300 CFG_VOUT1_D22_OUT pr2_pru0_gpo19
A10 vout1_d23 0 300 CFG_VOUT1_D23_OUT pr2_pru0_gpo20
G11 vout1_d3 0 1300 CFG_VOUT1_D3_OUT pr2_pru0_gpo0
E9 vout1_d4 0 2500 CFG_VOUT1_D4_OUT pr2_pru0_gpo1
F9 vout1_d5 0 950 CFG_VOUT1_D5_OUT pr2_pru0_gpo2
F8 vout1_d6 0 800 CFG_VOUT1_D6_OUT pr2_pru0_gpo3
E7 vout1_d7 0 600 CFG_VOUT1_D7_OUT pr2_pru0_gpo4
E8 vout1_d8 0 500 CFG_VOUT1_D8_OUT pr2_pru0_gpo5
D9 vout1_d9 0 500 CFG_VOUT1_D9_OUT pr2_pru0_gpo6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-165Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode for a definition of the Manual modes.

Table 7-165 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-165 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode

BALL BALL NAME PR2_PRU0_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
AC5 gpio6_10 1000 4100 CFG_GPIO6_10_OUT pr2_pru0_gpo0
AB4 gpio6_11 1000 4700 CFG_GPIO6_11_OUT pr2_pru0_gpo1
F14 mcasp1_axr15 0 1600 CFG_MCASP1_AXR15_OUT pr2_pru0_gpo20
A19 mcasp2_aclkx 0 2600 CFG_MCASP2_ACLKX_OUT pr2_pru0_gpo18
C15 mcasp2_axr2 0 1800 CFG_MCASP2_AXR2_OUT pr2_pru0_gpo16
A16 mcasp2_axr3 0 1200 CFG_MCASP2_AXR3_OUT pr2_pru0_gpo17
A18 mcasp2_fsx 0 0 CFG_MCASP2_FSX_OUT pr2_pru0_gpo19
B18 mcasp3_aclkx 0 2300 CFG_MCASP3_ACLKX_OUT pr2_pru0_gpo12
B19 mcasp3_axr0 0 300 CFG_MCASP3_AXR0_OUT pr2_pru0_gpo14
C17 mcasp3_axr1 0 600 CFG_MCASP3_AXR1_OUT pr2_pru0_gpo15
F15 mcasp3_fsx 0 500 CFG_MCASP3_FSX_OUT pr2_pru0_gpo13
AD4 mmc3_clk 1000 4400 CFG_MMC3_CLK_OUT pr2_pru0_gpo2
AC4 mmc3_cmd 1000 4300 CFG_MMC3_CMD_OUT pr2_pru0_gpo3
AC7 mmc3_dat0 1000 3400 CFG_MMC3_DAT0_OUT pr2_pru0_gpo4
AC6 mmc3_dat1 1000 3600 CFG_MMC3_DAT1_OUT pr2_pru0_gpo5
AC9 mmc3_dat2 1000 3400 CFG_MMC3_DAT2_OUT pr2_pru0_gpo6
AC3 mmc3_dat3 1000 3300 CFG_MMC3_DAT3_OUT pr2_pru0_gpo7
AC8 mmc3_dat4 1000 4300 CFG_MMC3_DAT4_OUT pr2_pru0_gpo8
AD6 mmc3_dat5 1000 4800 CFG_MMC3_DAT5_OUT pr2_pru0_gpo9
AB8 mmc3_dat6 1000 3900 CFG_MMC3_DAT6_OUT pr2_pru0_gpo10
AB5 mmc3_dat7 1000 4000 CFG_MMC3_DAT7_OUT pr2_pru0_gpo11

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-166Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode for a definition of the Manual modes.

Table 7-166 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-166 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode

BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
U3 RMII_MHZ_50_CLK 0 2100 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
U4 mdio_d 0 3200 CFG_MDIO_D_IN pr2_pru1_gpi1
V1 mdio_mclk 0 2422 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
U5 rgmii0_rxc 0 1904 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
V5 rgmii0_rxctl 0 3629 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
W2 rgmii0_rxd0 0 2800 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
Y2 rgmii0_rxd1 0 3100 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
V3 rgmii0_rxd2 0 2900 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
V4 rgmii0_rxd3 0 3363 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
W9 rgmii0_txc 0 2488 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
V9 rgmii0_txctl 0 2263 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
U6 rgmii0_txd0 0 2292 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
V6 rgmii0_txd1 0 2900 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
U7 rgmii0_txd2 0 2800 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
V7 rgmii0_txd3 0 2400 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
V2 uart3_rxd 0 1900 CFG_UART3_RXD_IN pr2_pru1_gpi3
Y1 uart3_txd 0 1900 CFG_UART3_TXD_IN pr2_pru1_gpi4
E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_IN pr2_pru1_gpi17
F11 vout1_d0 0 1020 CFG_VOUT1_D0_IN pr2_pru1_gpi18
G10 vout1_d1 0 976 CFG_VOUT1_D1_IN pr2_pru1_gpi19
F10 vout1_d2 0 946 CFG_VOUT1_D2_IN pr2_pru1_gpi20

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Input mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-167Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode for a definition of the Manual modes.

Table 7-167 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-167 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode

BALL BALL NAME PR2_PRU1_DIR_IN_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
C14 mcasp1_aclkx 0 700 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
G12 mcasp1_axr0 0 2100 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
F12 mcasp1_axr1 0 1250 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
B13 mcasp1_axr10 0 1800 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
A12 mcasp1_axr11 0 1700 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
E14 mcasp1_axr12 0 1000 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
A13 mcasp1_axr13 0 1300 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
G14 mcasp1_axr14 0 1200 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_IN pr2_pru1_gpi17
F11 vout1_d0 0 0 CFG_VOUT1_D0_IN pr2_pru1_gpi18
G10 vout1_d1 0 0 CFG_VOUT1_D1_IN pr2_pru1_gpi19
F10 vout1_d2 0 0 CFG_VOUT1_D2_IN pr2_pru1_gpi20
B12 mcasp1_axr8 0 1450 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
A11 mcasp1_axr9 0 1600 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
D17 mcasp4_axr1 0 1200 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
AA3 mcasp5_aclkx 800 4100 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
AB3 mcasp5_axr0 900 4100 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
AA4 mcasp5_axr1 1000 4100 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
AB9 mcasp5_fsx 800 3800 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
D18 xref_clk0 0 0 CFG_XREF_CLK0_IN pr2_pru1_gpi5
E17 xref_clk1 0 400 CFG_XREF_CLK1_IN pr2_pru1_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-168Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode for a definition of the Manual modes.

Table 7-168 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-168 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode

BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
U3 RMII_MHZ_50_CLK 0 2500 CFG_RMII_MHZ_50_CLK_OUT pr2_pru1_gpo2
U4 mdio_d 0 3900 CFG_MDIO_D_OUT pr2_pru1_gpo1
V1 mdio_mclk 0 3200 CFG_MDIO_MCLK_OUT pr2_pru1_gpo0
U5 rgmii0_rxc 0 2600 CFG_RGMII0_RXC_OUT pr2_pru1_gpo11
V5 rgmii0_rxctl 0 2800 CFG_RGMII0_RXCTL_OUT pr2_pru1_gpo12
W2 rgmii0_rxd0 0 2800 CFG_RGMII0_RXD0_OUT pr2_pru1_gpo16
Y2 rgmii0_rxd1 0 2700 CFG_RGMII0_RXD1_OUT pr2_pru1_gpo15
V3 rgmii0_rxd2 0 2600 CFG_RGMII0_RXD2_OUT pr2_pru1_gpo14
V4 rgmii0_rxd3 0 2700 CFG_RGMII0_RXD3_OUT pr2_pru1_gpo13
W9 rgmii0_txc 0 3300 CFG_RGMII0_TXC_OUT pr2_pru1_gpo5
V9 rgmii0_txctl 0 2700 CFG_RGMII0_TXCTL_OUT pr2_pru1_gpo6
U6 rgmii0_txd0 0 2900 CFG_RGMII0_TXD0_OUT pr2_pru1_gpo10
V6 rgmii0_txd1 0 2500 CFG_RGMII0_TXD1_OUT pr2_pru1_gpo9
U7 rgmii0_txd2 0 3000 CFG_RGMII0_TXD2_OUT pr2_pru1_gpo8
V7 rgmii0_txd3 0 3200 CFG_RGMII0_TXD3_OUT pr2_pru1_gpo7
V2 uart3_rxd 0 3400 CFG_UART3_RXD_OUT pr2_pru1_gpo3
Y1 uart3_txd 0 3000 CFG_UART3_TXD_OUT pr2_pru1_gpo4
F11 vout1_d0 0 600 CFG_VOUT1_D0_OUT pr2_pru1_gpo18
G10 vout1_d1 0 0 CFG_VOUT1_D1_OUT pr2_pru1_gpo19
F10 vout1_d2 0 300 CFG_VOUT1_D2_OUT pr2_pru1_gpo20
E11 vout1_vsync 0 1200 CFG_VOUT1_VSYNC_OUT pr2_pru1_gpo17

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Output mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-169Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode for a definition of the Manual modes.

Table 7-169 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-169 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode

BALL BALL NAME PR2_PRU1_DIR_OUT_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 13
C14 mcasp1_aclkx 0 1800 CFG_MCASP1_ACLKX_OUT pr2_pru1_gpo7
G12 mcasp1_axr0 0 800 CFG_MCASP1_AXR0_OUT pr2_pru1_gpo8
F12 mcasp1_axr1 0 1400 CFG_MCASP1_AXR1_OUT pr2_pru1_gpo9
B13 mcasp1_axr10 0 2300 CFG_MCASP1_AXR10_OUT pr2_pru1_gpo12
A12 mcasp1_axr11 0 600 CFG_MCASP1_AXR11_OUT pr2_pru1_gpo13
E14 mcasp1_axr12 0 700 CFG_MCASP1_AXR12_OUT pr2_pru1_gpo14
A13 mcasp1_axr13 0 1500 CFG_MCASP1_AXR13_OUT pr2_pru1_gpo15
G14 mcasp1_axr14 0 2000 CFG_MCASP1_AXR14_OUT pr2_pru1_gpo16
E11 vout1_vsync 0 0 CFG_VOUT1_VSYNC_OUT pr2_pru1_gpo17
F11 vout1_d0 0 0 CFG_VOUT1_D0_OUT pr2_pru1_gpo18
G10 vout1_d1 0 0 CFG_VOUT1_D1_OUT pr2_pru1_gpo19
F10 vout1_d2 0 0 CFG_VOUT1_D2_OUT pr2_pru1_gpo20
B12 mcasp1_axr8 0 2000 CFG_MCASP1_AXR8_OUT pr2_pru1_gpo10
A11 mcasp1_axr9 0 800 CFG_MCASP1_AXR9_OUT pr2_pru1_gpo11
D17 mcasp4_axr1 0 0 CFG_MCASP4_AXR1_OUT pr2_pru1_gpo0
AA3 mcasp5_aclkx 1000 4200 CFG_MCASP5_ACLKX_OUT pr2_pru1_gpo1
AB3 mcasp5_axr0 1000 3100 CFG_MCASP5_AXR0_OUT pr2_pru1_gpo3
AA4 mcasp5_axr1 1000 2700 CFG_MCASP5_AXR1_OUT pr2_pru1_gpo4
AB9 mcasp5_fsx 1000 2800 CFG_MCASP5_FSX_OUT pr2_pru1_gpo2
D18 xref_clk0 0 1600 CFG_XREF_CLK0_OUT pr2_pru1_gpo5
E17 xref_clk1 0 1500 CFG_XREF_CLK1_OUT pr2_pru1_gpo6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-170Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode for a definition of the Manual modes.

Table 7-170 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-170 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode

BALL BALL NAME PR2_PRU0_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
D7 vout1_d10 1554 0 CFG_VOUT1_D10_IN pr2_pru0_gpi7
D8 vout1_d11 1711 0 CFG_VOUT1_D11_IN pr2_pru0_gpi8
A5 vout1_d12 1562 0 CFG_VOUT1_D12_IN pr2_pru0_gpi9
C6 vout1_d13 1350 0 CFG_VOUT1_D13_IN pr2_pru0_gpi10
C8 vout1_d14 1552 0 CFG_VOUT1_D14_IN pr2_pru0_gpi11
C7 vout1_d15 1882 0 CFG_VOUT1_D15_IN pr2_pru0_gpi12
B7 vout1_d16 1525 0 CFG_VOUT1_D16_IN pr2_pru0_gpi13
B8 vout1_d17 1431 0 CFG_VOUT1_D17_IN pr2_pru0_gpi14
A7 vout1_d18 1240 0 CFG_VOUT1_D18_IN pr2_pru0_gpi15
A8 vout1_d19 0 0 CFG_VOUT1_D19_IN pr2_pru0_gpi16
G11 vout1_d3 1231 0 CFG_VOUT1_D3_IN pr2_pru0_gpi0
E9 vout1_d4 1355 0 CFG_VOUT1_D4_IN pr2_pru0_gpi1
F9 vout1_d5 1261 0 CFG_VOUT1_D5_IN pr2_pru0_gpi2
F8 vout1_d6 1016 0 CFG_VOUT1_D6_IN pr2_pru0_gpi3
E7 vout1_d7 1297 0 CFG_VOUT1_D7_IN pr2_pru0_gpi4
E8 vout1_d8 1390 0 CFG_VOUT1_D8_IN pr2_pru0_gpi5
D9 vout1_d9 1685 0 CFG_VOUT1_D9_IN pr2_pru0_gpi6

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU0 IOSET2 Parallel Capture mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-171Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture mode for a definition of the Manual modes.

Table 7-171 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-171 Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture mode

BALL BALL NAME PR2_PRU0_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
AC5 gpio6_10 3800 1785 CFG_GPIO6_10_IN pr2_pru0_gpi0
AB4 gpio6_11 3747 2246 CFG_GPIO6_11_IN pr2_pru0_gpi1
C15 mcasp2_axr2 0 0 CFG_MCASP2_AXR2_IN pr2_pru0_gpi16
B18 mcasp3_aclkx 271 0 CFG_MCASP3_ACLKX_IN pr2_pru0_gpi12
B19 mcasp3_axr0 1215 0 CFG_MCASP3_AXR0_IN pr2_pru0_gpi14
C17 mcasp3_axr1 1678 0 CFG_MCASP3_AXR1_IN pr2_pru0_gpi15
F15 mcasp3_fsx 1862 0 CFG_MCASP3_FSX_IN pr2_pru0_gpi13
AD4 mmc3_clk 3888 1913 CFG_MMC3_CLK_IN pr2_pru0_gpi2
AC4 mmc3_cmd 3804 1690 CFG_MMC3_CMD_IN pr2_pru0_gpi3
AC7 mmc3_dat0 3771 1681 CFG_MMC3_DAT0_IN pr2_pru0_gpi4
AC6 mmc3_dat1 3689 1591 CFG_MMC3_DAT1_IN pr2_pru0_gpi5
AC9 mmc3_dat2 3807 1441 CFG_MMC3_DAT2_IN pr2_pru0_gpi6
AC3 mmc3_dat3 3680 2415 CFG_MMC3_DAT3_IN pr2_pru0_gpi7
AC8 mmc3_dat4 3846 1455 CFG_MMC3_DAT4_IN pr2_pru0_gpi8
AD6 mmc3_dat5 3747 1673 CFG_MMC3_DAT5_IN pr2_pru0_gpi9
AB8 mmc3_dat6 3777 1557 CFG_MMC3_DAT6_IN pr2_pru0_gpi10
AB5 mmc3_dat7 3775 1320 CFG_MMC3_DAT7_IN pr2_pru0_gpi11

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET1 Parallel Capture mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-172Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture mode for a definition of the Manual modes.

Table 7-171 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-172 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture mode

BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
U3 RMII_MHZ_50_CLK 1234 0 CFG_RMII_MHZ_50_CLK_IN pr2_pru1_gpi2
U4 mdio_d 1693 0 CFG_MDIO_D_IN pr2_pru1_gpi1
V1 mdio_mclk 1045 0 CFG_MDIO_MCLK_IN pr2_pru1_gpi0
U5 rgmii0_rxc 1028 0 CFG_RGMII0_RXC_IN pr2_pru1_gpi11
V5 rgmii0_rxctl 1896 0 CFG_RGMII0_RXCTL_IN pr2_pru1_gpi12
W2 rgmii0_rxd0 0 0 CFG_RGMII0_RXD0_IN pr2_pru1_gpi16
Y2 rgmii0_rxd1 1659 0 CFG_RGMII0_RXD1_IN pr2_pru1_gpi15
V3 rgmii0_rxd2 1448 0 CFG_RGMII0_RXD2_IN pr2_pru1_gpi14
V4 rgmii0_rxd3 1762 0 CFG_RGMII0_RXD3_IN pr2_pru1_gpi13
W9 rgmii0_txc 1384 0 CFG_RGMII0_TXC_IN pr2_pru1_gpi5
V9 rgmii0_txctl 953 0 CFG_RGMII0_TXCTL_IN pr2_pru1_gpi6
U6 rgmii0_txd0 1170 0 CFG_RGMII0_TXD0_IN pr2_pru1_gpi10
V6 rgmii0_txd1 1749 0 CFG_RGMII0_TXD1_IN pr2_pru1_gpi9
U7 rgmii0_txd2 1410 0 CFG_RGMII0_TXD2_IN pr2_pru1_gpi8
V7 rgmii0_txd3 1479 0 CFG_RGMII0_TXD3_IN pr2_pru1_gpi7
V2 uart3_rxd 1124 0 CFG_UART3_RXD_IN pr2_pru1_gpi3
Y1 uart3_txd 765 0 CFG_UART3_TXD_IN pr2_pru1_gpi4

Manual IO Timings Modes must be used to ensure some IO timings for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode. See Table 7-2Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-173Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode for a definition of the Manual modes.

Table 7-173 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 7-173 Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode

BALL BALL NAME PR2_PRU1_PAR_CAP_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 12
C14 mcasp1_aclkx 1959 0 CFG_MCASP1_ACLKX_IN pr2_pru1_gpi7
G12 mcasp1_axr0 3142 0 CFG_MCASP1_AXR0_IN pr2_pru1_gpi8
F12 mcasp1_axr1 2361 0 CFG_MCASP1_AXR1_IN pr2_pru1_gpi9
B13 mcasp1_axr10 2488 0 CFG_MCASP1_AXR10_IN pr2_pru1_gpi12
A12 mcasp1_axr11 2652 0 CFG_MCASP1_AXR11_IN pr2_pru1_gpi13
E14 mcasp1_axr12 2036 0 CFG_MCASP1_AXR12_IN pr2_pru1_gpi14
A13 mcasp1_axr13 2301 0 CFG_MCASP1_AXR13_IN pr2_pru1_gpi15
G14 mcasp1_axr14 0 0 CFG_MCASP1_AXR14_IN pr2_pru1_gpi16
B12 mcasp1_axr8 2581 0 CFG_MCASP1_AXR8_IN pr2_pru1_gpi10
A11 mcasp1_axr9 2565 0 CFG_MCASP1_AXR9_IN pr2_pru1_gpi11
D17 mcasp4_axr1 2580 0 CFG_MCASP4_AXR1_IN pr2_pru1_gpi0
AA3 mcasp5_aclkx 3533 2482 CFG_MCASP5_ACLKX_IN pr2_pru1_gpi1
AB3 mcasp5_axr0 3568 2725 CFG_MCASP5_AXR0_IN pr2_pru1_gpi3
AA4 mcasp5_axr1 3679 2464 CFG_MCASP5_AXR1_IN pr2_pru1_gpi4
AB9 mcasp5_fsx 3604 2091 CFG_MCASP5_FSX_IN pr2_pru1_gpi2
D18 xref_clk0 851 0 CFG_XREF_CLK0_IN pr2_pru1_gpi5
E17 xref_clk1 1966 0 CFG_XREF_CLK1_IN pr2_pru1_gpi6
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