ZHCSG49F December   2015  – May 2019 AM5726 , AM5728 , AM5729

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Port (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface - (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timer
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  HDQ / 1-Wire Interface (HDQ1W)
      9. 4.4.9  Universal Asynchronous Receiver Transmitter (UART)
      10. 4.4.10 Multichannel Serial Peripheral Interface (McSPI)
      11. 4.4.11 Quad Serial Peripheral Interface (QSPI)
      12. 4.4.12 Multichannel Audio Serial Port (McASP)
      13. 4.4.13 Universal Serial Bus (USB)
      14. 4.4.14 Serial Advanced Technology Attachment (SATA)
      15. 4.4.15 Peripheral Component Interconnect Express (PCIe)
      16. 4.4.16 Controller Area Network Interface (DCAN)
      17. 4.4.17 Ethernet Interface (GMAC_SW)
      18. 4.4.18 Media Local Bus (MLB) Interface
      19. 4.4.19 eMMC/SD/SDIO
      20. 4.4.20 General-Purpose Interface (GPIO)
      21. 4.4.21 Keyboard controller (KBD)
      22. 4.4.22 Pulse Width Modulation (PWM)
      23. 4.4.23 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      24. 4.4.24 Test Interfaces
      25. 4.4.25 System and Miscellaneous
        1. 4.4.25.1 Sysboot
        2. 4.4.25.2 Power, Reset and Clock Management (PRCM)
        3. 4.4.25.3 Real-Time Clock (RTC) Interface
        4. 4.4.25.4 System Direct Memory Access (SDMA)
        5. 4.4.25.5 Interrupt Controllers (INTC)
        6. 4.4.25.6 Observability
        7. 4.4.25.7 Power Supplies
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hours (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  BC1833IHHV Buffers DC Electrical Characteristics
      8. 5.7.8  USBPHY DC Electrical Characteristics
      9. 5.7.9  Dual Voltage SDIO1833 DC Electrical Characteristics
      10. 5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics
      11. 5.7.11 SATAPHY DC Electrical Characteristics
      12. 5.7.12 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.13.1 HDQ / 1-Wire — HDQ Mode
      2. 7.13.2 HDQ/1-Wire—1-Wire Mode
    14. 7.14 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-41 Timing Requirements for UART
      2. Table 7-42 Switching Characteristics Over Recommended Operating Conditions for UART
    15. 7.15 Multichannel Serial Peripheral Interface (McSPI)
    16. 7.16 Quad Serial Peripheral Interface (QSPI)
    17. 7.17 Multichannel Audio Serial Port (McASP)
      1. Table 7-49 Timing Requirements for McASP1
      2. Table 7-50 Timing Requirements for McASP2
      3. Table 7-51 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-52 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-53 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-54 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    18. 7.18 Universal Serial Bus (USB)
      1. 7.18.1 USB1 DRD PHY
      2. 7.18.2 USB2 PHY
    19. 7.19 Serial Advanced Technology Attachment (SATA)
    20. 7.20 Peripheral Component Interconnect Express (PCIe)
    21. 7.21 Controller Area Network Interface (DCAN)
    22. 7.22 Ethernet Interface (GMAC_SW)
      1. 7.22.1 GMAC MII Timings
        1. Table 7-68 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-69 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-70 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-71 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.22.2 GMAC MDIO Interface Timings
      3. 7.22.3 GMAC RMII Timings
        1. Table 7-76 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-77 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-79 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.22.4 GMAC RGMII Timings
        1. Table 7-83 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-84 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-85 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-86 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    23. 7.23 eMMC/SD/SDIO
      1. 7.23.1 MMC1—SD Card Interface
        1. 7.23.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.23.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.23.1.3 SDR12, 4-bit data, half-cycle
        4. 7.23.1.4 SDR25, 4-bit data, half-cycle
        5. 7.23.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.23.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.23.1.7 UHS-I DDR50, 4-bit data
      2. 7.23.2 MMC2 — eMMC
        1. 7.23.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.23.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.23.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.23.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.23.3 MMC3 and MMC4—SDIO/SD
        1. 7.23.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.23.3.2 MMC3 and MMC4, SD High Speed
        3. 7.23.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.23.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.23.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    24. 7.24 General-Purpose Interface (GPIO)
    25. 7.25 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      1. 7.25.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.25.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-135 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-136 PRU-ICSS PRU Switching Requirements – Direct Output Mode
        2. 7.25.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-137 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        3. 7.25.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-138 PRU-ICSS PRU Timing Requirements – Shift In Mode
          2. Table 7-139 PRU-ICSS PRU Switching Requirements - Shift Out Mode
      2. 7.25.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.25.2.1 PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-140 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
          2. Table 7-141 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
          3. Table 7-142 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
          4. Table 7-143 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-144 PRU-ICSS ECAT Switching Requirements - Digital IOs
      3. 7.25.3 PRU-ICSS MII_RT and Switch
        1. 7.25.3.1 PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-145 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
          2. Table 7-146 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-147 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
        2. 7.25.3.2 PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-148 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
          2. Table 7-149 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-150 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-151 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.25.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-152 Timing Requirements for PRU-ICSS UART Receive
        2. Table 7-153 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      5. 7.25.5 PRU-ICSS IOSETs
      6. 7.25.6 PRU-ICSS Manual Functional Mapping
    26. 7.26 System and Miscellaneous interfaces
    27. 7.27 Test Interfaces
      1. 7.27.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.27.1.1 JTAG Electrical Data/Timing
          1. Table 7-174 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-175 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-176 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-177 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.27.2 Trace Port Interface Unit (TPIU)
        1. 7.27.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIFs
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High-Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Thermal Solution Guidance
    6. 8.6 Single-Ended Interfaces
      1. 8.6.1 General Routing Guidelines
      2. 8.6.2 QSPI Board Design and Layout Guidelines
    7. 8.7 LJCB_REFN/P Connections
    8. 8.8 Clock Routing Guidelines
      1. 8.8.1 32-kHz Oscillator Routing
      2. 8.8.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商标
    7. 9.7 静电放电警告
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABC|760
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.1 Power Supply Mapping

TPS659037 is the Power Management IC (PMIC) that should be used for the Device designs. TI requires use of this PMIC for the following reasons:

  • TI has validated its use with the Device
  • Board level margins including transient response and output accuracy are analyzed and optimized for the entire system
  • Support for power sequencing requirements (refer to Section 5.9Power Supply Sequences)
  • Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software

Whenever we allow for combining of rails mapped on any of the SMPSes, the PDN guidelines that are the most stringent of the rails combined should be implemented for the particular supply rail.

It is possible that some voltage domains on the device are unused in some systems. In such cases, to ensure device reliability, it is still required that the supply pins for the specific voltage domains are connected to some core power supply output.

These unused supplies though can be combined with any of the core supplies that are used (active) in the system. e.g. if IVA and GPU domains are not used, they can be combined with the CORE domain, thereby having a single power supply driving the combined CORE, IVA and GPU domains.

For the combined rail, the following relaxations do apply:

  • The AVS voltage of active rail in the combined rail needs to be used to set the power supply
  • The decoupling capacitance should be set according to the active rail in the combined rail

Table 8-1 illustrates the approved and validated power supply connections to the Device for the SMPS outputs of the TPS659037 PMIC.

Table 8-1 TPS659037 Power Supply Connections(1)

TPS659037 Power Supply Valid Combination 1 Valid Combination 2
SMPS1/2(2) vdd_mpu vdd_mpu
SMPS3 vdds_ddr1, vdds_ddr2 vdds_ddr1, vdds_ddr2
SMPS4/5 vdd_dspeve, vdd_gpu, vdd_iva vdd_dspeve
SMPS6 vdd vdd_gpu
SMPS7 SW configuration after boot vdd
SMPS8 vdds18v vdd_iva
SMPS9 SW configuration after boot 3.3V vddshvx
LDO1 vddshv8 vddshv8
LDO2 vddshv5 vdds18v
LDO3 vdda_usb1, vdda_usb2, vdda_usb3, vdda_sata vdda_usb1, vdda_usb2, vdda_usb3, vdda_sata
LDO4 vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1 vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_pcie1
LDO9 vdd_rtc vdd_rtc
LDOLN 1.8V PLLs 1.8V PLLs
LDOUSB vdda_usb3v3 vdda_usb3v3
  1. Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and peak) is within the limits of the PMIC for all rails of the device.
  2. Refer to the PMIC data manual for the latest TPS659037 specifications
  3. For more information on connectivity with the TPS659037 PMIC, see the TPS659037 User’s Guide to Power AM572x (SLIU011).
  4. A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj
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