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ZHCSG49F December 2015 – May 2019 AM5726 , AM5728 , AM5729

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8.2.2.10 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power, and processor/DDR ground connections. Table 8-9 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:

Fit as many HS bypass capacitors as possible.
Minimize the distance from the bypass cap to the pins/balls being bypassed.
Use the smallest physical sized capacitors possible with the highest capacitance readily available.
Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest hole size via possible.
Minimize via sharing. Note the limites on via sharing shown in Table 8-9.

Table 8-9 High-Speed Bypass Capacitors

NO.	PARAMETER	MIN	TYP	MAX	UNIT
1	HS bypass capacitor package size^⁽¹⁾		0201	0402	10 Mils
2	Distance, HS bypass capacitor to processor being bypassed^{⁽²⁾⁽³⁾⁽⁴⁾}			400	Mils
3	processor HS bypass capacitor count per vdds_ddrx rail ^⁽¹²⁾	See Section 8.4 and ^⁽¹¹⁾			Devices
4	processor HS bypass capacitor total capacitance per vdds_ddrx rail ^⁽¹²⁾	See Section 8.4 and ^⁽¹¹⁾			μF
5	Number of connection vias for each device power/ground ball^⁽⁵⁾				Vias
6	Trace length from device power/ground ball to connection via^⁽²⁾		35	70	Mils
7	Distance, HS bypass capacitor to DDR device being bypassed^⁽⁶⁾			150	Mils
8	DDR3 device HS bypass capacitor count^⁽⁷⁾	12			Devices
9	DDR3 device HS bypass capacitor total capacitance^⁽⁷⁾	0.85			μF
10	Number of connection vias for each HS capacitor^{⁽⁸⁾⁽⁹⁾}	2			Vias
11	Trace length from bypass capacitor connect to connection via^{⁽²⁾⁽⁹⁾}		35	100	Mils
12	Number of connection vias for each DDR3 device power/ground ball^⁽¹⁰⁾	1			Vias
13	Trace length from DDR3 device power/ground ball to connection via^{⁽²⁾⁽⁸⁾}		35	60	Mils

LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
Closer/shorter is better.
Measured from the nearest processor power/ground ball to the center of the capacitor package.
Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls, between the DDR interfaces on the package.
See the Via Channel™ escape for the processor package.
Measured from the DDR3 device power/ground ball to the center of the capacitor package.
Per DDR3 device.
An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
Up to a total of two pairs of DDR power/ground balls may share a via.
The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
For more information, see , Core Power Domains