ZHCSIM5F December 2016 – July 2018 AM5746 , AM5748 , AM5749
ADVANCE INFORMATION for pre-production products; subject to change without notice.
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information, see chapter Control Module of the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS1 PRU0 Direct Output mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-191, Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Output mode for a definition of the Manual modes.
Table 5-191 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR1_PRU0_DIR_OUT_MANUAL | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 13 | |||
AG3 | vin1a_d10 | 0 | 600 | CFG_VIN1A_D10_OUT | pr1_pru0_gpo7 |
AG5 | vin1a_d11 | 0 | 0 | CFG_VIN1A_D11_OUT | pr1_pru0_gpo8 |
AF2 | vin1a_d12 | 0 | 2400 | CFG_VIN1A_D12_OUT | pr1_pru0_gpo9 |
AF6 | vin1a_d13 | 0 | 200 | CFG_VIN1A_D13_OUT | pr1_pru0_gpo10 |
AF3 | vin1a_d14 | 0 | 900 | CFG_VIN1A_D14_OUT | pr1_pru0_gpo11 |
AF4 | vin1a_d15 | 0 | 0 | CFG_VIN1A_D15_OUT | pr1_pru0_gpo12 |
AF1 | vin1a_d16 | 0 | 100 | CFG_VIN1A_D16_OUT | pr1_pru0_gpo13 |
AE3 | vin1a_d17 | 0 | 300 | CFG_VIN1A_D17_OUT | pr1_pru0_gpo14 |
AE5 | vin1a_d18 | 0 | 0 | CFG_VIN1A_D18_OUT | pr1_pru0_gpo15 |
AE1 | vin1a_d19 | 0 | 400 | CFG_VIN1A_D19_OUT | pr1_pru0_gpo16 |
AE2 | vin1a_d20 | 0 | 300 | CFG_VIN1A_D20_OUT | pr1_pru0_gpo17 |
AE6 | vin1a_d21 | 0 | 500 | CFG_VIN1A_D21_OUT | pr1_pru0_gpo18 |
AD2 | vin1a_d22 | 0 | 0 | CFG_VIN1A_D22_OUT | pr1_pru0_gpo19 |
AD3 | vin1a_d23 | 0 | 500 | CFG_VIN1A_D23_OUT | pr1_pru0_gpo20 |
AH6 | vin1a_d3 | 0 | 1400 | CFG_VIN1A_D3_OUT | pr1_pru0_gpo0 |
AH3 | vin1a_d4 | 0 | 2600 | CFG_VIN1A_D4_OUT | pr1_pru0_gpo1 |
AH5 | vin1a_d5 | 0 | 0 | CFG_VIN1A_D5_OUT | pr1_pru0_gpo2 |
AG6 | vin1a_d6 | 0 | 0 | CFG_VIN1A_D6_OUT | pr1_pru0_gpo3 |
AH4 | vin1a_d7 | 0 | 0 | CFG_VIN1A_D7_OUT | pr1_pru0_gpo4 |
AG4 | vin1a_d8 | 0 | 0 | CFG_VIN1A_D8_OUT | pr1_pru0_gpo5 |
AG2 | vin1a_d9 | 0 | 300 | CFG_VIN1A_D9_OUT | pr1_pru0_gpo6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS1 PRU1 Direct Output mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-192, Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode for a definition of the Manual modes.
Table 5-192 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR1_PRU1_DIR_OUT_MANUAL | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 13 | |||
D3 | vin2a_d10 | 0 | 300 | CFG_VIN2A_D10_OUT | pr1_pru1_gpo7 |
F6 | vin2a_d11 | 0 | 800 | CFG_VIN2A_D11_OUT | pr1_pru1_gpo8 |
D5 | vin2a_d12 | 0 | 1800 | CFG_VIN2A_D12_OUT | pr1_pru1_gpo9 |
C2 | vin2a_d13 | 0 | 1600 | CFG_VIN2A_D13_OUT | pr1_pru1_gpo10 |
C3 | vin2a_d14 | 0 | 1400 | CFG_VIN2A_D14_OUT | pr1_pru1_gpo11 |
C4 | vin2a_d15 | 0 | 1300 | CFG_VIN2A_D15_OUT | pr1_pru1_gpo12 |
B2 | vin2a_d16 | 0 | 1100 | CFG_VIN2A_D16_OUT | pr1_pru1_gpo13 |
D6 | vin2a_d17 | 0 | 1400 | CFG_VIN2A_D17_OUT | pr1_pru1_gpo14 |
C5 | vin2a_d18 | 0 | 200 | CFG_VIN2A_D18_OUT | pr1_pru1_gpo15 |
A3 | vin2a_d19 | 0 | 600 | CFG_VIN2A_D19_OUT | pr1_pru1_gpo16 |
B3 | vin2a_d20 | 0 | 200 | CFG_VIN2A_D20_OUT | pr1_pru1_gpo17 |
B4 | vin2a_d21 | 0 | 0 | CFG_VIN2A_D21_OUT | pr1_pru1_gpo18 |
B5 | vin2a_d22 | 0 | 0 | CFG_VIN2A_D22_OUT | pr1_pru1_gpo19 |
A4 | vin2a_d23 | 0 | 0 | CFG_VIN2A_D23_OUT | pr1_pru1_gpo20 |
E2 | vin2a_d3 | 0 | 1700 | CFG_VIN2A_D3_OUT | pr1_pru1_gpo0 |
D2 | vin2a_d4 | 0 | 2800 | CFG_VIN2A_D4_OUT | pr1_pru1_gpo1 |
F4 | vin2a_d5 | 0 | 200 | CFG_VIN2A_D5_OUT | pr1_pru1_gpo2 |
C1 | vin2a_d6 | 0 | 1100 | CFG_VIN2A_D6_OUT | pr1_pru1_gpo3 |
E4 | vin2a_d7 | 0 | 1200 | CFG_VIN2A_D7_OUT | pr1_pru1_gpo4 |
F5 | vin2a_d8 | 0 | 1100 | CFG_VIN2A_D8_OUT | pr1_pru1_gpo5 |
E6 | vin2a_d9 | 0 | 700 | CFG_VIN2A_D9_OUT | pr1_pru1_gpo6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS1 PRU0 Direct Input mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-193, Manual Functions Mapping for PRU-ICSS1 PRU0 Direct Input mode for a definition of the Manual modes.
Table 5-193 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR1_PRU0_DIR_IN_MANUAL | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
AG3 | vin1a_d10 | 0 | 500 | CFG_VIN1A_D10_IN | pr1_pru0_gpi7 |
AG5 | vin1a_d11 | 0 | 0 | CFG_VIN1A_D11_IN | pr1_pru0_gpi8 |
AF2 | vin1a_d12 | 0 | 800 | CFG_VIN1A_D12_IN | pr1_pru0_gpi9 |
AF6 | vin1a_d13 | 0 | 300 | CFG_VIN1A_D13_IN | pr1_pru0_gpi10 |
AF3 | vin1a_d14 | 0 | 600 | CFG_VIN1A_D14_IN | pr1_pru0_gpi11 |
AF4 | vin1a_d15 | 0 | 1100 | CFG_VIN1A_D15_IN | pr1_pru0_gpi12 |
AF1 | vin1a_d16 | 0 | 800 | CFG_VIN1A_D16_IN | pr1_pru0_gpi13 |
AE3 | vin1a_d17 | 0 | 1000 | CFG_VIN1A_D17_IN | pr1_pru0_gpi14 |
AE5 | vin1a_d18 | 0 | 1100 | CFG_VIN1A_D18_IN | pr1_pru0_gpi15 |
AE1 | vin1a_d19 | 0 | 2500 | CFG_VIN1A_D19_IN | pr1_pru0_gpi16 |
AE2 | vin1a_d20 | 0 | 900 | CFG_VIN1A_D20_IN | pr1_pru0_gpi17 |
AE6 | vin1a_d21 | 0 | 800 | CFG_VIN1A_D21_IN | pr1_pru0_gpi18 |
AD2 | vin1a_d22 | 0 | 900 | CFG_VIN1A_D22_IN | pr1_pru0_gpi19 |
AD3 | vin1a_d23 | 0 | 500 | CFG_VIN1A_D23_IN | pr1_pru0_gpi20 |
AH6 | vin1a_d3 | 0 | 500 | CFG_VIN1A_D3_IN | pr1_pru0_gpi0 |
AH3 | vin1a_d4 | 0 | 0 | CFG_VIN1A_D4_IN | pr1_pru0_gpi1 |
AH5 | vin1a_d5 | 0 | 900 | CFG_VIN1A_D5_IN | pr1_pru0_gpi2 |
AG6 | vin1a_d6 | 0 | 400 | CFG_VIN1A_D6_IN | pr1_pru0_gpi3 |
AH4 | vin1a_d7 | 0 | 500 | CFG_VIN1A_D7_IN | pr1_pru0_gpi4 |
AG4 | vin1a_d8 | 0 | 0 | CFG_VIN1A_D8_IN | pr1_pru0_gpi5 |
AG2 | vin1a_d9 | 0 | 600 | CFG_VIN1A_D9_IN | pr1_pru0_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS1 PRU1 Direct Input mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-194, Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a definition of the Manual modes.
Table 5-194 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR1_PRU1_DIR_IN_MANUAL | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
D3 | vin2a_d10 | 0 | 1600 | CFG_VIN2A_D10_IN | pr1_pru1_gpi7 |
F6 | vin2a_d11 | 0 | 1000 | CFG_VIN2A_D11_IN | pr1_pru1_gpi8 |
D5 | vin2a_d12 | 0 | 1400 | CFG_VIN2A_D12_IN | pr1_pru1_gpi9 |
C2 | vin2a_d13 | 0 | 1000 | CFG_VIN2A_D13_IN | pr1_pru1_gpi10 |
C3 | vin2a_d14 | 0 | 0 | CFG_VIN2A_D14_IN | pr1_pru1_gpi11 |
C4 | vin2a_d15 | 0 | 1000 | CFG_VIN2A_D15_IN | pr1_pru1_gpi12 |
B2 | vin2a_d16 | 0 | 1200 | CFG_VIN2A_D16_IN | pr1_pru1_gpi13 |
D6 | vin2a_d17 | 0 | 1300 | CFG_VIN2A_D17_IN | pr1_pru1_gpi14 |
C5 | vin2a_d18 | 0 | 2000 | CFG_VIN2A_D18_IN | pr1_pru1_gpi15 |
A3 | vin2a_d19 | 0 | 1100 | CFG_VIN2A_D19_IN | pr1_pru1_gpi16 |
B3 | vin2a_d20 | 0 | 1700 | CFG_VIN2A_D20_IN | pr1_pru1_gpi17 |
B4 | vin2a_d21 | 0 | 1300 | CFG_VIN2A_D21_IN | pr1_pru1_gpi18 |
B5 | vin2a_d22 | 0 | 1200 | CFG_VIN2A_D22_IN | pr1_pru1_gpi19 |
A4 | vin2a_d23 | 0 | 1300 | CFG_VIN2A_D23_IN | pr1_pru1_gpi20 |
E2 | vin2a_d3 | 0 | 2100 | CFG_VIN2A_D3_IN | pr1_pru1_gpi0 |
D2 | vin2a_d4 | 0 | 1000 | CFG_VIN2A_D4_IN | pr1_pru1_gpi1 |
F4 | vin2a_d5 | 0 | 1700 | CFG_VIN2A_D5_IN | pr1_pru1_gpi2 |
C1 | vin2a_d6 | 0 | 700 | CFG_VIN2A_D6_IN | pr1_pru1_gpi3 |
E4 | vin2a_d7 | 0 | 1300 | CFG_VIN2A_D7_IN | pr1_pru1_gpi4 |
F5 | vin2a_d8 | 0 | 1700 | CFG_VIN2A_D8_IN | pr1_pru1_gpi5 |
E6 | vin2a_d9 | 0 | 1600 | CFG_VIN2A_D9_IN | pr1_pru1_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS1 PRU0 Parallel Capture mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-195, Manual Functions Mapping for PRU-ICSS1 PRU0 Parallel Capture mode for a definition of the Manual modes.
Table 5-195 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR1_PRU0_PAR_CAP_MANUAL | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
AG3 | vin1a_d10 | 516 | 0 | CFG_VIN1A_D10_IN | pr1_pru0_gpi7 |
AG5 | vin1a_d11 | 234 | 0 | CFG_VIN1A_D11_IN | pr1_pru0_gpi8 |
AF2 | vin1a_d12 | 586 | 0 | CFG_VIN1A_D12_IN | pr1_pru0_gpi9 |
AF6 | vin1a_d13 | 495 | 0 | CFG_VIN1A_D13_IN | pr1_pru0_gpi10 |
AF3 | vin1a_d14 | 643 | 0 | CFG_VIN1A_D14_IN | pr1_pru0_gpi11 |
AF4 | vin1a_d15 | 715 | 0 | CFG_VIN1A_D15_IN | pr1_pru0_gpi12 |
AF1 | vin1a_d16 | 590 | 0 | CFG_VIN1A_D16_IN | pr1_pru0_gpi13 |
AE3 | vin1a_d17 | 713 | 0 | CFG_VIN1A_D17_IN | pr1_pru0_gpi14 |
AE5 | vin1a_d18 | 669 | 0 | CFG_VIN1A_D18_IN | pr1_pru0_gpi15 |
AE1 | vin1a_d19 | 0 | 0 | CFG_VIN1A_D19_IN | pr1_pru0_gpi16 |
AH6 | vin1a_d3 | 363 | 0 | CFG_VIN1A_D3_IN | pr1_pru0_gpi0 |
AH3 | vin1a_d4 | 391 | 0 | CFG_VIN1A_D4_IN | pr1_pru0_gpi1 |
AH5 | vin1a_d5 | 471 | 0 | CFG_VIN1A_D5_IN | pr1_pru0_gpi2 |
AG6 | vin1a_d6 | 386 | 0 | CFG_VIN1A_D6_IN | pr1_pru0_gpi3 |
AH4 | vin1a_d7 | 351 | 0 | CFG_VIN1A_D7_IN | pr1_pru0_gpi4 |
AG4 | vin1a_d8 | 360 | 0 | CFG_VIN1A_D8_IN | pr1_pru0_gpi5 |
AG2 | vin1a_d9 | 669 | 0 | CFG_VIN1A_D9_IN | pr1_pru0_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS1 PRU1 Parallel Capture mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-196, Manual Functions Mapping for PRU-ICSS1 PRU1 Parallel Capture mode for a definition of the Manual modes.
Table 5-196 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR1_PRU1_PAR_CAP_MANUAL | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
D3 | vin2a_d10 | 2410 | 799 | CFG_VIN2A_D10_IN | pr1_pru1_gpi7 |
F6 | vin2a_d11 | 2305 | 173 | CFG_VIN2A_D11_IN | pr1_pru1_gpi8 |
D5 | vin2a_d12 | 2261 | 513 | CFG_VIN2A_D12_IN | pr1_pru1_gpi9 |
C2 | vin2a_d13 | 2507 | 244 | CFG_VIN2A_D13_IN | pr1_pru1_gpi10 |
C3 | vin2a_d14 | 1992 | 0 | CFG_VIN2A_D14_IN | pr1_pru1_gpi11 |
C4 | vin2a_d15 | 2379 | 209 | CFG_VIN2A_D15_IN | pr1_pru1_gpi12 |
B2 | vin2a_d16 | 2278 | 339 | CFG_VIN2A_D16_IN | pr1_pru1_gpi13 |
D6 | vin2a_d17 | 2290 | 448 | CFG_VIN2A_D17_IN | pr1_pru1_gpi14 |
C5 | vin2a_d18 | 2546 | 1185 | CFG_VIN2A_D18_IN | pr1_pru1_gpi15 |
A3 | vin2a_d19 | 0 | 0 | CFG_VIN2A_D19_IN | pr1_pru1_gpi16 |
E2 | vin2a_d3 | 2651 | 685 | CFG_VIN2A_D3_IN | pr1_pru1_gpi0 |
D2 | vin2a_d4 | 2379 | 0 | CFG_VIN2A_D4_IN | pr1_pru1_gpi1 |
F4 | vin2a_d5 | 2607 | 747 | CFG_VIN2A_D5_IN | pr1_pru1_gpi2 |
C1 | vin2a_d6 | 2141 | 0 | CFG_VIN2A_D6_IN | pr1_pru1_gpi3 |
E4 | vin2a_d7 | 2339 | 441 | CFG_VIN2A_D7_IN | pr1_pru1_gpi4 |
F5 | vin2a_d8 | 2396 | 663 | CFG_VIN2A_D8_IN | pr1_pru1_gpi5 |
E6 | vin2a_d9 | 2384 | 443 | CFG_VIN2A_D9_IN | pr1_pru1_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Input mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-197, Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Input mode for a definition of the Manual modes.
Table 5-197 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU0_DIR_IN_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
D7 | vout1_d10 | 0 | 100 | CFG_VOUT1_D10_IN | pr2_pru0_gpi7 |
D8 | vout1_d11 | 0 | 756 | CFG_VOUT1_D11_IN | pr2_pru0_gpi8 |
A5 | vout1_d12 | 0 | 531 | CFG_VOUT1_D12_IN | pr2_pru0_gpi9 |
C6 | vout1_d13 | 0 | 180 | CFG_VOUT1_D13_IN | pr2_pru0_gpi10 |
C8 | vout1_d14 | 0 | 334 | CFG_VOUT1_D14_IN | pr2_pru0_gpi11 |
C7 | vout1_d15 | 0 | 1060 | CFG_VOUT1_D15_IN | pr2_pru0_gpi12 |
B7 | vout1_d16 | 0 | 488 | CFG_VOUT1_D16_IN | pr2_pru0_gpi13 |
B8 | vout1_d17 | 0 | 400 | CFG_VOUT1_D17_IN | pr2_pru0_gpi14 |
A7 | vout1_d18 | 0 | 254 | CFG_VOUT1_D18_IN | pr2_pru0_gpi15 |
A8 | vout1_d19 | 0 | 500 | CFG_VOUT1_D19_IN | pr2_pru0_gpi16 |
C9 | vout1_d20 | 0 | 716 | CFG_VOUT1_D20_IN | pr2_pru0_gpi17 |
A9 | vout1_d21 | 0 | 400 | CFG_VOUT1_D21_IN | pr2_pru0_gpi18 |
B9 | vout1_d22 | 0 | 404 | CFG_VOUT1_D22_IN | pr2_pru0_gpi19 |
A10 | vout1_d23 | 0 | 290 | CFG_VOUT1_D23_IN | pr2_pru0_gpi20 |
G11 | vout1_d3 | 0 | 226 | CFG_VOUT1_D3_IN | pr2_pru0_gpi0 |
E9 | vout1_d4 | 0 | 0 | CFG_VOUT1_D4_IN | pr2_pru0_gpi1 |
F9 | vout1_d5 | 0 | 365 | CFG_VOUT1_D5_IN | pr2_pru0_gpi2 |
F8 | vout1_d6 | 0 | 0 | CFG_VOUT1_D6_IN | pr2_pru0_gpi3 |
E7 | vout1_d7 | 0 | 218 | CFG_VOUT1_D7_IN | pr2_pru0_gpi4 |
E8 | vout1_d8 | 0 | 400 | CFG_VOUT1_D8_IN | pr2_pru0_gpi5 |
D9 | vout1_d9 | 0 | 500 | CFG_VOUT1_D9_IN | pr2_pru0_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Input mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-198, Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Input mode for a definition of the Manual modes.
Table 5-198 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU0_DIR_IN_MANUAL2 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
AC5 | gpio6_10 | 1000 | 4200 | CFG_GPIO6_10_IN | pr2_pru0_gpi0 |
AB4 | gpio6_11 | 1000 | 4400 | CFG_GPIO6_11_IN | pr2_pru0_gpi1 |
F14 | mcasp1_axr15 | 0 | 1300 | CFG_MCASP1_AXR15_IN | pr2_pru0_gpi20 |
A19 | mcasp2_aclkx | 0 | 700 | CFG_MCASP2_ACLKX_IN | pr2_pru0_gpi18 |
C15 | mcasp2_axr2 | 0 | 1800 | CFG_MCASP2_AXR2_IN | pr2_pru0_gpi16 |
A16 | mcasp2_axr3 | 0 | 1400 | CFG_MCASP2_AXR3_IN | pr2_pru0_gpi17 |
A18 | mcasp2_fsx | 0 | 900 | CFG_MCASP2_FSX_IN | pr2_pru0_gpi19 |
B18 | mcasp3_aclkx | 0 | 0 | CFG_MCASP3_ACLKX_IN | pr2_pru0_gpi12 |
B19 | mcasp3_axr0 | 0 | 1200 | CFG_MCASP3_AXR0_IN | pr2_pru0_gpi14 |
C17 | mcasp3_axr1 | 0 | 1200 | CFG_MCASP3_AXR1_IN | pr2_pru0_gpi15 |
F15 | mcasp3_fsx | 0 | 1400 | CFG_MCASP3_FSX_IN | pr2_pru0_gpi13 |
AD4 | mmc3_clk | 1000 | 4400 | CFG_MMC3_CLK_IN | pr2_pru0_gpi2 |
AC4 | mmc3_cmd | 1000 | 4100 | CFG_MMC3_CMD_IN | pr2_pru0_gpi3 |
AC7 | mmc3_dat0 | 1000 | 4200 | CFG_MMC3_DAT0_IN | pr2_pru0_gpi4 |
AC6 | mmc3_dat1 | 1000 | 4500 | CFG_MMC3_DAT1_IN | pr2_pru0_gpi5 |
AC9 | mmc3_dat2 | 1000 | 4200 | CFG_MMC3_DAT2_IN | pr2_pru0_gpi6 |
AC3 | mmc3_dat3 | 1000 | 4500 | CFG_MMC3_DAT3_IN | pr2_pru0_gpi7 |
AC8 | mmc3_dat4 | 1000 | 3800 | CFG_MMC3_DAT4_IN | pr2_pru0_gpi8 |
AD6 | mmc3_dat5 | 1000 | 4300 | CFG_MMC3_DAT5_IN | pr2_pru0_gpi9 |
AB8 | mmc3_dat6 | 1000 | 4200 | CFG_MMC3_DAT6_IN | pr2_pru0_gpi10 |
AB5 | mmc3_dat7 | 1000 | 3700 | CFG_MMC3_DAT7_IN | pr2_pru0_gpi11 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU0 IOSET1 Direct Output mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-199, Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Direct Output mode for a definition of the Manual modes.
Table 5-199 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU0_DIR_OUT_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 13 | |||
D7 | vout1_d10 | 0 | 0 | CFG_VOUT1_D10_OUT | pr2_pru0_gpo7 |
D8 | vout1_d11 | 0 | 500 | CFG_VOUT1_D11_OUT | pr2_pru0_gpo8 |
A5 | vout1_d12 | 0 | 1600 | CFG_VOUT1_D12_OUT | pr2_pru0_gpo9 |
C6 | vout1_d13 | 0 | 250 | CFG_VOUT1_D13_OUT | pr2_pru0_gpo10 |
C8 | vout1_d14 | 0 | 300 | CFG_VOUT1_D14_OUT | pr2_pru0_gpo11 |
C7 | vout1_d15 | 0 | 300 | CFG_VOUT1_D15_OUT | pr2_pru0_gpo12 |
B7 | vout1_d16 | 0 | 0 | CFG_VOUT1_D16_OUT | pr2_pru0_gpo13 |
B8 | vout1_d17 | 0 | 100 | CFG_VOUT1_D17_OUT | pr2_pru0_gpo14 |
A7 | vout1_d18 | 0 | 500 | CFG_VOUT1_D18_OUT | pr2_pru0_gpo15 |
A8 | vout1_d19 | 0 | 500 | CFG_VOUT1_D19_OUT | pr2_pru0_gpo16 |
C9 | vout1_d20 | 0 | 700 | CFG_VOUT1_D20_OUT | pr2_pru0_gpo17 |
A9 | vout1_d21 | 0 | 500 | CFG_VOUT1_D21_OUT | pr2_pru0_gpo18 |
B9 | vout1_d22 | 0 | 100 | CFG_VOUT1_D22_OUT | pr2_pru0_gpo19 |
A10 | vout1_d23 | 0 | 100 | CFG_VOUT1_D23_OUT | pr2_pru0_gpo20 |
G11 | vout1_d3 | 0 | 800 | CFG_VOUT1_D3_OUT | pr2_pru0_gpo0 |
E9 | vout1_d4 | 0 | 2000 | CFG_VOUT1_D4_OUT | pr2_pru0_gpo1 |
F9 | vout1_d5 | 0 | 550 | CFG_VOUT1_D5_OUT | pr2_pru0_gpo2 |
F8 | vout1_d6 | 0 | 600 | CFG_VOUT1_D6_OUT | pr2_pru0_gpo3 |
E7 | vout1_d7 | 0 | 400 | CFG_VOUT1_D7_OUT | pr2_pru0_gpo4 |
E8 | vout1_d8 | 0 | 100 | CFG_VOUT1_D8_OUT | pr2_pru0_gpo5 |
D9 | vout1_d9 | 0 | 500 | CFG_VOUT1_D9_OUT | pr2_pru0_gpo6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU0 IOSET2 Direct Output mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-200, Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Direct Output mode for a definition of the Manual modes.
Table 5-200 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU0_DIR_OUT_MANUAL2 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 13 | |||
AC5 | gpio6_10 | 1000 | 3800 | CFG_GPIO6_10_OUT | pr2_pru0_gpo0 |
AB4 | gpio6_11 | 1000 | 4400 | CFG_GPIO6_11_OUT | pr2_pru0_gpo1 |
F14 | mcasp1_axr15 | 0 | 1300 | CFG_MCASP1_AXR15_OUT | pr2_pru0_gpo20 |
A19 | mcasp2_aclkx | 0 | 2500 | CFG_MCASP2_ACLKX_OUT | pr2_pru0_gpo18 |
C15 | mcasp2_axr2 | 0 | 1800 | CFG_MCASP2_AXR2_OUT | pr2_pru0_gpo16 |
A16 | mcasp2_axr3 | 0 | 1200 | CFG_MCASP2_AXR3_OUT | pr2_pru0_gpo17 |
A18 | mcasp2_fsx | 0 | 0 | CFG_MCASP2_FSX_OUT | pr2_pru0_gpo19 |
B18 | mcasp3_aclkx | 0 | 2300 | CFG_MCASP3_ACLKX_OUT | pr2_pru0_gpo12 |
B19 | mcasp3_axr0 | 0 | 300 | CFG_MCASP3_AXR0_OUT | pr2_pru0_gpo14 |
C17 | mcasp3_axr1 | 0 | 400 | CFG_MCASP3_AXR1_OUT | pr2_pru0_gpo15 |
F15 | mcasp3_fsx | 0 | 400 | CFG_MCASP3_FSX_OUT | pr2_pru0_gpo13 |
AD4 | mmc3_clk | 1000 | 4100 | CFG_MMC3_CLK_OUT | pr2_pru0_gpo2 |
AC4 | mmc3_cmd | 1000 | 4200 | CFG_MMC3_CMD_OUT | pr2_pru0_gpo3 |
AC7 | mmc3_dat0 | 1000 | 3400 | CFG_MMC3_DAT0_OUT | pr2_pru0_gpo4 |
AC6 | mmc3_dat1 | 1000 | 3600 | CFG_MMC3_DAT1_OUT | pr2_pru0_gpo5 |
AC9 | mmc3_dat2 | 1000 | 3900 | CFG_MMC3_DAT2_OUT | pr2_pru0_gpo6 |
AC3 | mmc3_dat3 | 1000 | 3700 | CFG_MMC3_DAT3_OUT | pr2_pru0_gpo7 |
AC8 | mmc3_dat4 | 1000 | 4400 | CFG_MMC3_DAT4_OUT | pr2_pru0_gpo8 |
AD6 | mmc3_dat5 | 1000 | 4600 | CFG_MMC3_DAT5_OUT | pr2_pru0_gpo9 |
AB8 | mmc3_dat6 | 1000 | 4200 | CFG_MMC3_DAT6_OUT | pr2_pru0_gpo10 |
AB5 | mmc3_dat7 | 1000 | 4000 | CFG_MMC3_DAT7_OUT | pr2_pru0_gpo11 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Input mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-201, Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Input mode for a definition of the Manual modes.
Table 5-201 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU1_DIR_IN_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
U3 | RMII_MHZ_50_CLK | 0 | 2500 | CFG_RMII_MHZ_50_CLK_IN | pr2_pru1_gpi2 |
U4 | mdio_d | 0 | 3000 | CFG_MDIO_D_IN | pr2_pru1_gpi1 |
V1 | mdio_mclk | 0 | 2422 | CFG_MDIO_MCLK_IN | pr2_pru1_gpi0 |
U5 | rgmii0_rxc | 0 | 1904 | CFG_RGMII0_RXC_IN | pr2_pru1_gpi11 |
V5 | rgmii0_rxctl | 0 | 3000 | CFG_RGMII0_RXCTL_IN | pr2_pru1_gpi12 |
W2 | rgmii0_rxd0 | 0 | 2800 | CFG_RGMII0_RXD0_IN | pr2_pru1_gpi16 |
Y2 | rgmii0_rxd1 | 0 | 3100 | CFG_RGMII0_RXD1_IN | pr2_pru1_gpi15 |
V3 | rgmii0_rxd2 | 0 | 2800 | CFG_RGMII0_RXD2_IN | pr2_pru1_gpi14 |
V4 | rgmii0_rxd3 | 0 | 3100 | CFG_RGMII0_RXD3_IN | pr2_pru1_gpi13 |
W9 | rgmii0_txc | 0 | 2488 | CFG_RGMII0_TXC_IN | pr2_pru1_gpi5 |
V9 | rgmii0_txctl | 0 | 2263 | CFG_RGMII0_TXCTL_IN | pr2_pru1_gpi6 |
U6 | rgmii0_txd0 | 0 | 2292 | CFG_RGMII0_TXD0_IN | pr2_pru1_gpi10 |
V6 | rgmii0_txd1 | 0 | 2900 | CFG_RGMII0_TXD1_IN | pr2_pru1_gpi9 |
U7 | rgmii0_txd2 | 0 | 2600 | CFG_RGMII0_TXD2_IN | pr2_pru1_gpi8 |
V7 | rgmii0_txd3 | 0 | 2600 | CFG_RGMII0_TXD3_IN | pr2_pru1_gpi7 |
V2 | uart3_rxd | 0 | 1900 | CFG_UART3_RXD_IN | pr2_pru1_gpi3 |
Y1 | uart3_txd | 0 | 1900 | CFG_UART3_TXD_IN | pr2_pru1_gpi4 |
F11 | vout1_d0 | 0 | 1300 | CFG_VOUT1_D0_IN | pr2_pru1_gpi18 |
G10 | vout1_d1 | 0 | 1300 | CFG_VOUT1_D1_IN | pr2_pru1_gpi19 |
F10 | vout1_d2 | 0 | 1100 | CFG_VOUT1_D2_IN | pr2_pru1_gpi20 |
E11 | vout1_vsync | 0 | 0 | CFG_VOUT1_VSYNC_IN | pr2_pru1_gpi17 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Input mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-202, Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Input mode for a definition of the Manual modes.
Table 5-202 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU1_DIR_IN_MANUAL2 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
C14 | mcasp1_aclkx | 0 | 900 | CFG_MCASP1_ACLKX_IN | pr2_pru1_gpi7 |
G12 | mcasp1_axr0 | 0 | 1900 | CFG_MCASP1_AXR0_IN | pr2_pru1_gpi8 |
F12 | mcasp1_axr1 | 0 | 1250 | CFG_MCASP1_AXR1_IN | pr2_pru1_gpi9 |
B13 | mcasp1_axr10 | 0 | 1600 | CFG_MCASP1_AXR10_IN | pr2_pru1_gpi12 |
A12 | mcasp1_axr11 | 0 | 1700 | CFG_MCASP1_AXR11_IN | pr2_pru1_gpi13 |
E14 | mcasp1_axr12 | 0 | 1000 | CFG_MCASP1_AXR12_IN | pr2_pru1_gpi14 |
A13 | mcasp1_axr13 | 0 | 1300 | CFG_MCASP1_AXR13_IN | pr2_pru1_gpi15 |
G14 | mcasp1_axr14 | 0 | 1200 | CFG_MCASP1_AXR14_IN | pr2_pru1_gpi16 |
B12 | mcasp1_axr8 | 0 | 1450 | CFG_MCASP1_AXR8_IN | pr2_pru1_gpi10 |
A11 | mcasp1_axr9 | 0 | 1600 | CFG_MCASP1_AXR9_IN | pr2_pru1_gpi11 |
D17 | mcasp4_axr1 | 0 | 1600 | CFG_MCASP4_AXR1_IN | pr2_pru1_gpi0 |
AA3 | mcasp5_aclkx | 800 | 3900 | CFG_MCASP5_ACLKX_IN | pr2_pru1_gpi1 |
AB3 | mcasp5_axr0 | 1100 | 4200 | CFG_MCASP5_AXR0_IN | pr2_pru1_gpi3 |
AA4 | mcasp5_axr1 | 1200 | 4200 | CFG_MCASP5_AXR1_IN | pr2_pru1_gpi4 |
AB9 | mcasp5_fsx | 1000 | 3800 | CFG_MCASP5_FSX_IN | pr2_pru1_gpi2 |
F11 | vout1_d0 | 0 | 0 | CFG_VOUT1_D0_IN | pr2_pru1_gpi18 |
G10 | vout1_d1 | 0 | 0 | CFG_VOUT1_D1_IN | pr2_pru1_gpi19 |
F10 | vout1_d2 | 0 | 0 | CFG_VOUT1_D2_IN | pr2_pru1_gpi20 |
E11 | vout1_vsync | 0 | 0 | CFG_VOUT1_VSYNC_IN | pr2_pru1_gpi17 |
D18 | xref_clk0 | 0 | 0 | CFG_XREF_CLK0_IN | pr2_pru1_gpi5 |
E17 | xref_clk1 | 0 | 750 | CFG_XREF_CLK1_IN | pr2_pru1_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU1 IOSET1 Direct Output mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-203, Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Direct Output mode for a definition of the Manual modes.
Table 5-203 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU1_DIR_OUT_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 13 | |||
U3 | RMII_MHZ_50_CLK | 0 | 2600 | CFG_RMII_MHZ_50_CLK_OUT | pr2_pru1_gpo2 |
U4 | mdio_d | 0 | 3600 | CFG_MDIO_D_OUT | pr2_pru1_gpo1 |
V1 | mdio_mclk | 0 | 3000 | CFG_MDIO_MCLK_OUT | pr2_pru1_gpo0 |
U5 | rgmii0_rxc | 0 | 2700 | CFG_RGMII0_RXC_OUT | pr2_pru1_gpo11 |
V5 | rgmii0_rxctl | 0 | 2800 | CFG_RGMII0_RXCTL_OUT | pr2_pru1_gpo12 |
W2 | rgmii0_rxd0 | 0 | 2800 | CFG_RGMII0_RXD0_OUT | pr2_pru1_gpo16 |
Y2 | rgmii0_rxd1 | 0 | 2600 | CFG_RGMII0_RXD1_OUT | pr2_pru1_gpo15 |
V3 | rgmii0_rxd2 | 0 | 2800 | CFG_RGMII0_RXD2_OUT | pr2_pru1_gpo14 |
V4 | rgmii0_rxd3 | 0 | 2700 | CFG_RGMII0_RXD3_OUT | pr2_pru1_gpo13 |
W9 | rgmii0_txc | 0 | 3500 | CFG_RGMII0_TXC_OUT | pr2_pru1_gpo5 |
V9 | rgmii0_txctl | 0 | 2700 | CFG_RGMII0_TXCTL_OUT | pr2_pru1_gpo6 |
U6 | rgmii0_txd0 | 0 | 3200 | CFG_RGMII0_TXD0_OUT | pr2_pru1_gpo10 |
V6 | rgmii0_txd1 | 0 | 2700 | CFG_RGMII0_TXD1_OUT | pr2_pru1_gpo9 |
U7 | rgmii0_txd2 | 0 | 3100 | CFG_RGMII0_TXD2_OUT | pr2_pru1_gpo8 |
V7 | rgmii0_txd3 | 0 | 3200 | CFG_RGMII0_TXD3_OUT | pr2_pru1_gpo7 |
V2 | uart3_rxd | 0 | 3400 | CFG_UART3_RXD_OUT | pr2_pru1_gpo3 |
Y1 | uart3_txd | 0 | 2700 | CFG_UART3_TXD_OUT | pr2_pru1_gpo4 |
F11 | vout1_d0 | 0 | 600 | CFG_VOUT1_D0_OUT | pr2_pru1_gpo18 |
G10 | vout1_d1 | 0 | 0 | CFG_VOUT1_D1_OUT | pr2_pru1_gpo19 |
F10 | vout1_d2 | 0 | 200 | CFG_VOUT1_D2_OUT | pr2_pru1_gpo20 |
E11 | vout1_vsync | 0 | 1200 | CFG_VOUT1_VSYNC_OUT | pr2_pru1_gpo17 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU1 IOSET2 Direct Output mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-204, Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Direct Output mode for a definition of the Manual modes.
Table 5-204 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU1_DIR_OUT_MANUAL2 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 13 | |||
C14 | mcasp1_aclkx | 0 | 1800 | CFG_MCASP1_ACLKX_OUT | pr2_pru1_gpo7 |
G12 | mcasp1_axr0 | 0 | 1000 | CFG_MCASP1_AXR0_OUT | pr2_pru1_gpo8 |
F12 | mcasp1_axr1 | 0 | 1400 | CFG_MCASP1_AXR1_OUT | pr2_pru1_gpo9 |
B13 | mcasp1_axr10 | 0 | 2300 | CFG_MCASP1_AXR10_OUT | pr2_pru1_gpo12 |
A12 | mcasp1_axr11 | 0 | 900 | CFG_MCASP1_AXR11_OUT | pr2_pru1_gpo13 |
E14 | mcasp1_axr12 | 0 | 1000 | CFG_MCASP1_AXR12_OUT | pr2_pru1_gpo14 |
A13 | mcasp1_axr13 | 0 | 1500 | CFG_MCASP1_AXR13_OUT | pr2_pru1_gpo15 |
G14 | mcasp1_axr14 | 0 | 2000 | CFG_MCASP1_AXR14_OUT | pr2_pru1_gpo16 |
B12 | mcasp1_axr8 | 0 | 2000 | CFG_MCASP1_AXR8_OUT | pr2_pru1_gpo10 |
A11 | mcasp1_axr9 | 0 | 800 | CFG_MCASP1_AXR9_OUT | pr2_pru1_gpo11 |
D17 | mcasp4_axr1 | 0 | 0 | CFG_MCASP4_AXR1_OUT | pr2_pru1_gpo0 |
AA3 | mcasp5_aclkx | 1000 | 3900 | CFG_MCASP5_ACLKX_OUT | pr2_pru1_gpo1 |
AB3 | mcasp5_axr0 | 1000 | 3500 | CFG_MCASP5_AXR0_OUT | pr2_pru1_gpo3 |
AA4 | mcasp5_axr1 | 1000 | 2600 | CFG_MCASP5_AXR1_OUT | pr2_pru1_gpo4 |
AB9 | mcasp5_fsx | 1000 | 2800 | CFG_MCASP5_FSX_OUT | pr2_pru1_gpo2 |
F11 | vout1_d0 | 0 | 0 | CFG_VOUT1_D0_OUT | pr2_pru1_gpo18 |
G10 | vout1_d1 | 0 | 0 | CFG_VOUT1_D1_OUT | pr2_pru1_gpo19 |
F10 | vout1_d2 | 0 | 0 | CFG_VOUT1_D2_OUT | pr2_pru1_gpo20 |
E11 | vout1_vsync | 0 | 0 | CFG_VOUT1_VSYNC_OUT | pr2_pru1_gpo17 |
D18 | xref_clk0 | 0 | 1600 | CFG_XREF_CLK0_OUT | pr2_pru1_gpo5 |
E17 | xref_clk1 | 0 | 1200 | CFG_XREF_CLK1_OUT | pr2_pru1_gpo6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-205, Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET1 Parallel Capture mode for a definition of the Manual modes.
Table 5-205 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU0_PAR_CAP_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
D7 | vout1_d10 | 1472 | 0 | CFG_VOUT1_D10_IN | pr2_pru0_gpi7 |
D8 | vout1_d11 | 1601 | 0 | CFG_VOUT1_D11_IN | pr2_pru0_gpi8 |
A5 | vout1_d12 | 1488 | 0 | CFG_VOUT1_D12_IN | pr2_pru0_gpi9 |
C6 | vout1_d13 | 1447 | 0 | CFG_VOUT1_D13_IN | pr2_pru0_gpi10 |
C8 | vout1_d14 | 1265 | 0 | CFG_VOUT1_D14_IN | pr2_pru0_gpi11 |
C7 | vout1_d15 | 1738 | 0 | CFG_VOUT1_D15_IN | pr2_pru0_gpi12 |
B7 | vout1_d16 | 1411 | 0 | CFG_VOUT1_D16_IN | pr2_pru0_gpi13 |
B8 | vout1_d17 | 1753 | 0 | CFG_VOUT1_D17_IN | pr2_pru0_gpi14 |
A7 | vout1_d18 | 1214 | 0 | CFG_VOUT1_D18_IN | pr2_pru0_gpi15 |
A8 | vout1_d19 | 0 | 0 | CFG_VOUT1_D19_IN | pr2_pru0_gpi16 |
G11 | vout1_d3 | 1581 | 0 | CFG_VOUT1_D3_IN | pr2_pru0_gpi0 |
E9 | vout1_d4 | 1242 | 0 | CFG_VOUT1_D4_IN | pr2_pru0_gpi1 |
F9 | vout1_d5 | 1250 | 0 | CFG_VOUT1_D5_IN | pr2_pru0_gpi2 |
F8 | vout1_d6 | 1273 | 0 | CFG_VOUT1_D6_IN | pr2_pru0_gpi3 |
E7 | vout1_d7 | 1278 | 0 | CFG_VOUT1_D7_IN | pr2_pru0_gpi4 |
E8 | vout1_d8 | 1742 | 0 | CFG_VOUT1_D8_IN | pr2_pru0_gpi5 |
D9 | vout1_d9 | 1823 | 0 | CFG_VOUT1_D9_IN | pr2_pru0_gpi6 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU0 IOSET2 Parallel Capture mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-206, Manual Functions Mapping for PRU-ICSS2 PRU0 IOSET2 Parallel Capture mode for a definition of the Manual modes.
Table 5-206 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU0_PAR_CAP_MANUAL2 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
AC5 | gpio6_10 | 3958 | 1843 | CFG_GPIO6_10_IN | pr2_pru0_gpi0 |
AB4 | gpio6_11 | 3922 | 1888 | CFG_GPIO6_11_IN | pr2_pru0_gpi1 |
C15 | mcasp2_axr2 | 0 | 0 | CFG_MCASP2_AXR2_IN | pr2_pru0_gpi16 |
B18 | mcasp3_aclkx | 173 | 0 | CFG_MCASP3_ACLKX_IN | pr2_pru0_gpi12 |
B19 | mcasp3_axr0 | 1396 | 0 | CFG_MCASP3_AXR0_IN | pr2_pru0_gpi14 |
C17 | mcasp3_axr1 | 1752 | 0 | CFG_MCASP3_AXR1_IN | pr2_pru0_gpi15 |
F15 | mcasp3_fsx | 1651 | 0 | CFG_MCASP3_FSX_IN | pr2_pru0_gpi13 |
AD4 | mmc3_clk | 4001 | 1940 | CFG_MMC3_CLK_IN | pr2_pru0_gpi2 |
AC4 | mmc3_cmd | 3960 | 1772 | CFG_MMC3_CMD_IN | pr2_pru0_gpi3 |
AC7 | mmc3_dat0 | 3907 | 1751 | CFG_MMC3_DAT0_IN | pr2_pru0_gpi4 |
AC6 | mmc3_dat1 | 3804 | 2185 | CFG_MMC3_DAT1_IN | pr2_pru0_gpi5 |
AC9 | mmc3_dat2 | 3911 | 1810 | CFG_MMC3_DAT2_IN | pr2_pru0_gpi6 |
AC3 | mmc3_dat3 | 3898 | 2167 | CFG_MMC3_DAT3_IN | pr2_pru0_gpi7 |
AC8 | mmc3_dat4 | 3974 | 1487 | CFG_MMC3_DAT4_IN | pr2_pru0_gpi8 |
AD6 | mmc3_dat5 | 3895 | 1926 | CFG_MMC3_DAT5_IN | pr2_pru0_gpi9 |
AB8 | mmc3_dat6 | 3939 | 1802 | CFG_MMC3_DAT6_IN | pr2_pru0_gpi10 |
AB5 | mmc3_dat7 | 3961 | 1278 | CFG_MMC3_DAT7_IN | pr2_pru0_gpi11 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU1 IOSET1 Parallel Capture mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-207, Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET1 Parallel Capture mode for a definition of the Manual modes.
Table 5-206 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU1_PAR_CAP_MANUAL1 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
U3 | RMII_MHZ_50_CLK | 1214 | 0 | CFG_RMII_MHZ_50_CLK_IN | pr2_pru1_gpi2 |
U5 | rgmii0_rxc | 787 | 0 | CFG_RGMII0_RXC_IN | pr2_pru1_gpi11 |
V5 | rgmii0_rxctl | 1554 | 0 | CFG_RGMII0_RXCTL_IN | pr2_pru1_gpi12 |
W2 | rgmii0_rxd0 | 0 | 0 | CFG_RGMII0_RXD0_IN | pr2_pru1_gpi16 |
Y2 | rgmii0_rxd1 | 1212 | 0 | CFG_RGMII0_RXD1_IN | pr2_pru1_gpi15 |
V3 | rgmii0_rxd2 | 1145 | 0 | CFG_RGMII0_RXD2_IN | pr2_pru1_gpi14 |
V4 | rgmii0_rxd3 | 1492 | 0 | CFG_RGMII0_RXD3_IN | pr2_pru1_gpi13 |
W9 | rgmii0_txc | 823 | 0 | CFG_RGMII0_TXC_IN | pr2_pru1_gpi5 |
V9 | rgmii0_txctl | 833 | 0 | CFG_RGMII0_TXCTL_IN | pr2_pru1_gpi6 |
U6 | rgmii0_txd0 | 886 | 0 | CFG_RGMII0_TXD0_IN | pr2_pru1_gpi10 |
V6 | rgmii0_txd1 | 1350 | 0 | CFG_RGMII0_TXD1_IN | pr2_pru1_gpi9 |
U7 | rgmii0_txd2 | 1026 | 0 | CFG_RGMII0_TXD2_IN | pr2_pru1_gpi8 |
V7 | rgmii0_txd3 | 1366 | 0 | CFG_RGMII0_TXD3_IN | pr2_pru1_gpi7 |
V2 | uart3_rxd | 922 | 0 | CFG_UART3_RXD_IN | pr2_pru1_gpi3 |
Y1 | uart3_txd | 604 | 0 | CFG_UART3_TXD_IN | pr2_pru1_gpi4 |
U4 | mdio_d | 1192 | 0 | CFG_MDIO_D_IN | pr2_pru1_gpi1 |
V1 | mdio_mclk | 819 | 0 | CFG_MDIO_MCLK_IN | pr2_pru1_gpi0 |
Manual IO Timings Modes must be used to guarantee some IO timings for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode. See Table 5-33, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-208, Manual Functions Mapping for PRU-ICSS2 PRU1 IOSET2 Parallel Capture mode for a definition of the Manual modes.
Table 5-208 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | PR2_PRU1_PAR_CAP_MANUAL2 | CFG REGISTER | MUXMODE | |
---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | 12 | |||
C14 | mcasp1_aclkx | 1460 | 0 | CFG_MCASP1_ACLKX_IN | pr2_pru1_gpi7 |
G12 | mcasp1_axr0 | 2613 | 0 | CFG_MCASP1_AXR0_IN | pr2_pru1_gpi8 |
F12 | mcasp1_axr1 | 1765 | 0 | CFG_MCASP1_AXR1_IN | pr2_pru1_gpi9 |
B13 | mcasp1_axr10 | 1990 | 0 | CFG_MCASP1_AXR10_IN | pr2_pru1_gpi12 |
A12 | mcasp1_axr11 | 2333 | 0 | CFG_MCASP1_AXR11_IN | pr2_pru1_gpi13 |
E14 | mcasp1_axr12 | 1680 | 0 | CFG_MCASP1_AXR12_IN | pr2_pru1_gpi14 |
A13 | mcasp1_axr13 | 1681 | 0 | CFG_MCASP1_AXR13_IN | pr2_pru1_gpi15 |
G14 | mcasp1_axr14 | 0 | 0 | CFG_MCASP1_AXR14_IN | pr2_pru1_gpi16 |
B12 | mcasp1_axr8 | 2063 | 0 | CFG_MCASP1_AXR8_IN | pr2_pru1_gpi10 |
A11 | mcasp1_axr9 | 1979 | 0 | CFG_MCASP1_AXR9_IN | pr2_pru1_gpi11 |
D17 | mcasp4_axr1 | 2303 | 0 | CFG_MCASP4_AXR1_IN | pr2_pru1_gpi0 |
AA3 | mcasp5_aclkx | 3735 | 1700 | CFG_MCASP5_ACLKX_IN | pr2_pru1_gpi1 |
AB3 | mcasp5_axr0 | 3729 | 2308 | CFG_MCASP5_AXR0_IN | pr2_pru1_gpi3 |
AA4 | mcasp5_axr1 | 3731 | 2345 | CFG_MCASP5_AXR1_IN | pr2_pru1_gpi4 |
AB9 | mcasp5_fsx | 3700 | 1877 | CFG_MCASP5_FSX_IN | pr2_pru1_gpi2 |
D18 | xref_clk0 | 130 | 0 | CFG_XREF_CLK0_IN | pr2_pru1_gpi5 |
E17 | xref_clk1 | 1552 | 0 | CFG_XREF_CLK1_IN | pr2_pru1_gpi6 |