6.14 EDMA

The primary purpose of the Enhanced Direct Memory Access (EDMA) controller is to service user-programmed data transfers between two memory-mapped slave endpoints on the device.

Typical usage of the EDMA controller includes:

• Servicing software-driven paging transfers (for example, data movement between external memory [such as SDRAM] and internal memory [such as DSP L2 SRAM])
• Servicing event-driven peripherals, such as a serial port
• Performing sorting or sub-frame extraction of various data structures
• Offloading data transfers from the main device CPUs, such as the C66x DSP CorePac or the Arm CorePac

The EDMA controller consists of two major principle blocks:

• EDMA Channel Controller
• EDMA Transfer Controller(s)

The EDMA Channel Controller (EDMACC) serves as the user interface for the EDMA controller. The EDMACC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers. The EDMACC serves to prioritize incoming software requests or events from peripherals and submits transfer requests (TR) to the EDMA transfer controller.

The EDMA Transfer Controller (EDMATC) is responsible for data movement. The transfer request packets (TRP) submitted by the EDMACC contain the transfer context, based on which the transfer controller issues read/write commands to the source and destination addresses programmed for a given transfer.

There are two EDMA controllers present on this device:

• EDMA_0, integrating:
  • 1 Channel Controller, referenced as: EDMACC_0
  • 2 Transfer Controllers, referenced as: EDMACC_0_TC_0 (or EDMATC_0) and EDMACC_0_TC_1 (or EDMATC_1)
• EDMA_1, integrating:
  • 1 Channel Controller, referenced as: EDMACC_1
  • 2 Transfer Controllers, referenced as: EDMACC_1_TC_0 (or EDMATC_2) and EDMACC_1_TC_1 (or EDMATC_3)

The two EDMA channel controllers (EDMACC_0 and EDMACC_1) are functionally identical. For simplification, the unified name EDMACC shall be regularly used throughout this chapter when referring to EDMA Channel Controllers functionality and features.

The four EDMA transfer controllers (EDMACC_0_TC_0, EDMACC_0_TC_1, EDMACC_1_TC_0 and EDMACC_1_TC_1) are functionally identical. For simplification, the unified name EDMATC shall be regularly used throughout this chapter when referring to EDMA Transfer Controllers functionality and features.

Each EDMACC has the following features:

• Fully orthogonal transfer description
  • 3 transfer dimensions:
    • Array (multiple bytes)
    • Frame (multiple arrays)
    • Block (multiple frames)
  • Single event can trigger transfer of array, frame, or entire block
  • Independent indexes on source and destination
• Flexible transfer definition
  • Increment or constant addressing modes
  • Linking mechanism allows automatic PaRAM set update
  • Chaining allows multiple transfers to execute with one event
• 64 DMA channels
  • Channels triggered by either:
    • Event synchronization
    • Manual synchronization (CPU write to event set register)
    • Chain synchronization (completion of one transfer triggers another transfer)
  • Support for programmable DMA Channel to PaRAM mapping
• 8 Quick DMA (QDMA) channels
  • QDMA channels are triggered automatically upon writing to PaRAM set entry
  • Support for programmable QDMA channel to PaRAM mapping
• 512 PaRAM sets
  • Each PaRAM set can be used for a DMA channel, QDMA channel, or link set
• 2 transfer controllers/event queues
  • 16 event entries per event queue
• Interrupt generation based on:
  • Transfer completion
  • Error conditions
• Debug visibility
  • Queue water marking/threshold
  • Error and status recording to facilitate debug
• Memory protection support
  • Proxied memory protection for TR submission
  • Active memory protection for accesses to PaRAM and registers

Each EDMATC has the following features:

• Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC manages the 3rd dimension)
• Up to 4 in-flight transfer requests (TR)
• Programmable priority levels
• Support for increment or constant addressing mode transfers
• Interrupt and error support
• Supports only little-endian operation in this device
• Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR

For more information, see section Enhanced DMA in chapter DMA Controllers of the Device TRM.