Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from off-chip power-sources.

There is one PLL in the MCU domain:

• MCU PLL

There are nine PLLs in the MAIN domain:

• MAIN PLL
• PER0 PLL
• PER1 PLL
• VIDEO PLL
• C7x PLL
• ARM0 PLL
• DDR PLL
• SMS PLL
• DSS PLL

The system designer should consider the reference clock source start-up time and the PLL lock requirements before configuring and using any of the PLL outputs as clock sources. The device reference clock input requirements are defined in Section 7.10.4.1, Input Clocks / Oscillators. PLL configuration details are described in the device TRM.

For more information on PLLs, see the PLL subsection in the Clocking subsection of the Device Configuration section in the device TRM.