米6体育平台手机版

ZHCSLA7C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
O1	t_c(CLK)	Cycle time, CLK		19		ns
O2	t_w(CLKL)	Pulse duration, CLK low		-0.3+0.475×P ⁽²⁾		ns
O3	t_w(CLKH)	Pulse duration, CLK high		-0.3+0.475×P ⁽²⁾		ns
O4	t_d(CLK-CSn)	Delay time, CSn active edge to CLK rising edge	1.8 V	0.475 × P + 0.975 × N × R ⁽²⁾⁽³⁾⁽⁵⁾	0.475 × P + 0.975 × N × R + 7.7 ⁽²⁾⁽³⁾⁽⁵⁾	ns
O4	t_d(CLK-CSn)	Delay time, CSn active edge to CLK rising edge	3.3 V	0.475 × P + 0.975 × N × R ⁽²⁾⁽³⁾⁽⁵⁾	0.475 × P + 0.975 × N × R + 8 ⁽²⁾⁽³⁾⁽⁵⁾	ns
O5	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	1.8 V	0.475 × P + 0.975 × N × R - 7.7⁽²⁾⁽⁴⁾⁽⁵⁾	0.475 × P + 0.975 × N × R ⁽²⁾⁽⁴⁾⁽⁵⁾	ns
O5	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	3.3 V	0.475 × P + 0.975 × N × R - 8⁽²⁾⁽⁴⁾⁽⁵⁾	0.475 × P + 0.975 × N × R ⁽²⁾ ⁽⁴⁾⁽⁵⁾	ns
O6	t_d(CLK-D)	Delay time, CLK active edge to D[i:0]⁽¹⁾ transition	1.8 V	-7.7	-1.56	ns
O6	t_d(CLK-D)	Delay time, CLK active edge to D[i:0]⁽¹⁾ transition	3.3 V	-7.7	-1.56	ns

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) P = CLK cycle time = SCLK period

(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5) R = refclk

Figure 6-90 OSPI Switching Characteristics - DDR

For more information, see section Octal Serial Peripheral Interface (OSPI) in the device TRM.