米6体育平台手机版

ZHCSLA7C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

NO.	DESCRIPTION⁽¹⁾		MODE	MIN	MAX	UNIT
O7	t_c(CLK)	Cycle time, CLK	1.8V	7		ns
O7	t_c(CLK)	Cycle time, CLK	3.3V	7.52		ns
O8	t_w(CLKL)	Pulse duration, CLK low		-0.3+0.475×P ⁽¹⁾		ns
O9	t_w(CLKH)	Pulse duration, CLK high		-0.3+0.475×P ⁽¹⁾		ns
O10	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn active edge	1.8V	0.475 × P + 0.975 × N × R - 1⁽¹⁾ ⁽²⁾ ⁽⁴⁾	0.475 × P + 0.975 × N × R + 1 ⁽¹⁾ ⁽²⁾ ⁽⁴⁾	ns
O10	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn active edge	3.3V	0.475 × P + 0.975 × N × R - 1⁽¹⁾ ⁽²⁾ ⁽⁴⁾	0.475 × P + 0.975 × N × R + 1 ⁽¹⁾ ⁽²⁾ ⁽⁴⁾	ns
O11	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	1.8V	0.475 × P + 0.975 × N × R - 1 ⁽¹⁾⁽³⁾ ⁽⁴⁾	0.475 × P + 0.975 × N × R ⁽¹⁾ ⁽³⁾ ⁽⁴⁾	ns
O11	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	3.3V	0.475 × P + 0.975 × N × R - 1⁽¹⁾ ⁽³⁾ ⁽⁴⁾	0.475 × P + 0.975 × N × R + 1 ⁽¹⁾ ⁽³⁾ ⁽⁴⁾	ns
O12	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition	1.8V	-1.15	1.25	ns
O12	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition	3.3V	-1.33	1.51	ns

(1) P = CLK cycle time = SCLK period

(2) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4) R = refclk

Figure 6-88 OSPI Switching Characteristics - SDR

Section 6.9.5.18.2.3, Section 6.9.5.18.2.1, Figure 6-89, and Figure 6-87 presents timing requirements for OSPI DDR and SDR Mode.