ZHCSLA7C December   2019  – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  CAL
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  CPSW2G
        1. 5.3.3.1 MCU Domain
      4. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 DDRSS Mapping
      5. 5.3.5  DMTIMER
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
      7. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
      8. 5.3.8  EHRPWM
        1. 5.3.8.1 MAIN Domain
      9. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
      10. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
        2. 5.3.10.2 WKUP Domain
      11. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 HyperBus
        1. 5.3.12.1 MCU Domain
      13. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
        2. 5.3.13.2 MCU Domain
        3. 5.3.13.3 WKUP Domain
      14. 5.3.14 MCAN
        1. 5.3.14.1 MCU Domain
      15. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
        2. 5.3.16.2 MCU Domain
      17. 5.3.17 MMCSD
        1. 5.3.17.1 MAIN Domain
      18. 5.3.18 CPTS
        1. 5.3.18.1 MCU Domain
        2. 5.3.18.2 MAIN Domain
      19. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 OSPI
        1. 5.3.20.1 MCU Domain
      21. 5.3.21 PRU_ICSSG
        1. 5.3.21.1 MAIN Domain
      22. 5.3.22 SERDES
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
        2. 5.3.23.2 MCU Domain
        3. 5.3.23.3 WKUP Domain
      24. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 Emulation and Debug
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 System and Miscellaneous
        1. 5.3.26.1 Boot Mode Configuration
          1. 5.3.26.1.1 MAIN Domain
          2. 5.3.26.1.2 MCU Domain
        2. 5.3.26.2 Clock
          1. 5.3.26.2.1 MAIN Domain
          2. 5.3.26.2.2 WKUP Domain
        3. 5.3.26.3 System
          1. 5.3.26.3.1 MAIN Domain
          2. 5.3.26.3.2 WKUP Domain
        4. 5.3.26.4 Miscellaneous
          1. 5.3.26.4.1 WKUP Domain
        5. 5.3.26.5 EFUSE
          1. 5.3.26.5.1 MAIN Domain
          2. 5.3.26.5.2 MCU Domain
      27. 5.3.27 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On Hours (POH)
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
      1. 6.5.1 Voltage and Core Clock Specifications
    6. 6.6 Electrical Characteristics
      1. 6.6.1 I2C OPEN DRAIN DC Electrical Characteristics
      2. 6.6.2 Analog OSC Buffers DC Electrical Characteristics
      3. 6.6.3 Analog ADC DC Electrical Characteristics
      4. 6.6.4 DPHY CSI2 Buffers DC Electrical Characteristics
      5. 6.6.5 OLDI LVDS Buffers DC Electrical Characteristics
        1. 6.6.5.1 LVCMOS Buffers DC Electrical Characteristics
      6. 6.6.6 USBHS Buffers DC Electrical Characteristics
      7. 6.6.7 SERDES Buffers DC Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement
        3. 6.9.2.3 Power-Up Sequencing
        4. 6.9.2.4 Power-Down Sequencing
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Electrical Data/Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source
          8. 6.9.4.1.8 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 6.9.4.5 Module and Peripheral Clock Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  VIN
        2. 6.9.5.2  CPSW2G
          1. 6.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.2.2 CPSW2G RMII Timings
            1. 6.9.5.2.2.1 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. 6.9.5.2.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. 6.9.5.2.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 6.9.5.2.3 CPSW2G RGMII Timings
            1. 6.9.5.2.3.1 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. 6.9.5.2.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. 6.9.5.2.3.3 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. 6.9.5.2.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode
        3. 6.9.5.3  CSI2
        4. 6.9.5.4  DDRSS
        5. 6.9.5.5  DSS
        6. 6.9.5.6  eCAP
          1. 6.9.5.6.1 eCAP Timing Requirements
          2. 6.9.5.6.2 eCAP Switching Characteristics
        7. 6.9.5.7  ePWM
          1. 6.9.5.7.1 ePWM Timing Requirements
          2. 6.9.5.7.2 ePWM Switching Characteristics
        8. 6.9.5.8  eQEP
          1. 6.9.5.8.1 eQEP Timing Requirements
          2. 6.9.5.8.2 eQEP Switching Characteristics
        9. 6.9.5.9  GPIO
          1. 6.9.5.9.1 GPIO Timing Requirements
          2. 6.9.5.9.2 GPIO Switching Characteristics
        10. 6.9.5.10 GPMC
          1. 6.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. 6.9.5.10.1.1 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. 6.9.5.10.1.2 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 6.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. 6.9.5.10.2.1 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.2.2 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 6.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. 6.9.5.10.3.1 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.3.2 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 6.9.5.11 HyperBus
          1. 6.9.5.11.1 Timing Requirements for HyperBus Initialization
          2. 6.9.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.9.5.12 I2C
        13. 6.9.5.13 MCAN
        14. 6.9.5.14 MCASP
          1. 6.9.5.14.1 MCASP Timing Requirements and Switching Characteristics
        15. 6.9.5.15 MCSPI
          1. 6.9.5.15.1 SPI—Master Mode
          2. 6.9.5.15.2 SPI—Slave Mode
        16. 6.9.5.16 MMCSD
          1. 6.9.5.16.1 MMCSDi — eMMC/SD/SDIO Card Interface
            1. 6.9.5.16.1.1 Default Speed, 3.3V Legacy SDR Mode
            2. 6.9.5.16.1.2 High Speed, 3.3V High Speed SDR Mode
            3. 6.9.5.16.1.3 UHS-I SDR12, 1.8-V Legacy SDR Mode
            4. 6.9.5.16.1.4 UHS-I SDR25 Mode
            5. 6.9.5.16.1.5 UHS-I DDR50 Mode
            6. 6.9.5.16.1.6 UHS-I SDR50 Mode
            7. 6.9.5.16.1.7 UHS-I SDR104 / HS200 Mode
        17. 6.9.5.17 CPTS
          1. 6.9.5.17.1 CPTS Timing Requirements
          2. 6.9.5.17.2 CPTS Switching Characteristics
        18. 6.9.5.18 OSPI
          1. 6.9.5.18.1 OSPI with Data Training
            1. 6.9.5.18.1.1 OSPI Switching Characteristics - Data Training
          2. 6.9.5.18.2 OSPI without Data Training
            1. 6.9.5.18.2.1 OSPI Timing Requirements - SDR Mode
            2. 6.9.5.18.2.2 OSPI Switching Characteristics - SDR Mode
            3. 6.9.5.18.2.3 OSPI Timing Requirements - DDR Mode
            4. 6.9.5.18.2.4 OSPI Switching Characteristics - DDR Mode
        19. 6.9.5.19 OLDI
          1. 6.9.5.19.1 OLDI Switching Characteristics
        20. 6.9.5.20 PCIE
        21. 6.9.5.21 PRU_ICSSG
          1. 6.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 6.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. 6.9.5.21.1.1.1 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 6.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. 6.9.5.21.1.2.1 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 6.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. 6.9.5.21.1.3.1 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. 6.9.5.21.1.3.2 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 6.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. 6.9.5.21.1.4.1 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. 6.9.5.21.1.4.2 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. 6.9.5.21.1.4.3 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 6.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. 6.9.5.21.2.1.1 PRU_ICSSG PWM Switching Characteristics
          3. 6.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 6.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. 6.9.5.21.3.1.1 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. 6.9.5.21.3.1.2 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. 6.9.5.21.3.1.3 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 6.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 6.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. 6.9.5.21.4.1.1 PRU_ICSSG UART Timing Requirements
              2. 6.9.5.21.4.1.2 PRU_ICSSG UART Switching Characteristics
          5. 6.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 6.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. 6.9.5.21.5.1.1 PRU_ICSSG ECAP Timing Requirements
              2. 6.9.5.21.5.1.2 PRU_ICSSG ECAP Switching Characteristics
          6. 6.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. 6.9.5.21.6.1.1 PRU_ICSSG MDIO Timing Requirements
              2. 6.9.5.21.6.1.2 PRU_ICSSG MDIO Switching Characteristics - MDIO_CLK
              3. 6.9.5.21.6.1.3 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 6.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. 6.9.5.21.6.2.1 PRU_ICSSG RGMII Timing Requirements - RGMII_RXC
              2. 6.9.5.21.6.2.2 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RX_CTL
              3. 6.9.5.21.6.2.3 PRU_ICSSG RGMII Switching Characteristics - RGMII_TXC
              4. 6.9.5.21.6.2.4 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL
            3. 6.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. 6.9.5.21.6.3.1 PRU_ICSSG MII_RT Timing Requirements – MII_RX_CLK
              2. 6.9.5.21.6.3.2 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RX_DV, and MII_RX_ER
              3. 6.9.5.21.6.3.3 PRU_ICSSG MII_RT Switching Characteristics – MII_TX_CLK
              4. 6.9.5.21.6.3.4 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 6.9.5.22 Timers
          1. 6.9.5.22.1 Timing Requirements for Timers
          2. 6.9.5.22.2 Switching Characteristics for Timers
        23. 6.9.5.23 UART
          1. 6.9.5.23.1 Timing Requirements for UART
          2. 6.9.5.23.2 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 6.9.5.24 USB
        25. 6.9.5.25 Emulation and Debug
          1. 6.9.5.25.1 Debug Trace
          2. 6.9.5.25.2 JTAG
            1. 6.9.5.25.2.1 JTAG Electrical Data and Timing
              1. 6.9.5.25.2.1.1 JTAG Timing Requirements
              2. 6.9.5.25.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53
      2. 7.2.2 Arm Cortex-R5F
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 PRU_ICSSG
        1. 7.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores
        2. 7.3.1.2 PRU_ICSSG Broadside Accelerators Overview
        3. 7.3.1.3 PRU_ICSSG UART Module
        4. 7.3.1.4 PRU_ICSSG ECAP Module
        5. 7.3.1.5 PRU_ICSSG PWM Module
        6. 7.3.1.6 PRU_ICSSG MII_G_RT Module
        7. 7.3.1.7 PRU_ICSSG MII MDIO Module
        8. 7.3.1.8 PRU_ICSSG IEP
      2. 7.3.2 GPU
    4. 7.4 Other Subsystems
      1. 7.4.1 DMSC
      2. 7.4.2 MSMC
      3. 7.4.3 NAVSS
        1. 7.4.3.1 NAVSS0
        2. 7.4.3.2 MCU_NAVSS0
      4. 7.4.4 PDMA Controller
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  CAL
        3. 7.4.5.3  CPSW2G
        4. 7.4.5.4  DCC
        5. 7.4.5.5  DDRSS
        6. 7.4.5.6  DSS
        7. 7.4.5.7  ЕCAP
        8. 7.4.5.8  EPWM
        9. 7.4.5.9  ELM
        10. 7.4.5.10 ESM
        11. 7.4.5.11 EQEP
        12. 7.4.5.12 GPIO
        13. 7.4.5.13 GPMC
        14. 7.4.5.14 HyperBus
        15. 7.4.5.15 I2C
        16. 7.4.5.16 MCAN
        17. 7.4.5.17 MCASP
        18. 7.4.5.18 MCRC
        19. 7.4.5.19 MCSPI
        20. 7.4.5.20 MMCSD
        21. 7.4.5.21 OSPI
        22. 7.4.5.22 PCIE
        23. 7.4.5.23 SerDes
        24. 7.4.5.24 RTI
        25. 7.4.5.25 Timers
        26. 7.4.5.26 UART
        27. 7.4.5.27 USB
    5. 7.5 Identification
      1. 7.5.1 Revision Identification
      2. 7.5.2 Die Identification
      3. 7.5.3 JTAG Identification
      4. 7.5.4 ROM Code Identification
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG and EMU
      4. 8.1.4 Reset
      5. 8.1.5 Unused Pins
      6. 8.1.6 Hardware Design Guide for AM65x/DRA80xM Devices
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (Only Available in Octal Flash Devices)
      3. 8.2.3 USB Design Guidelines
      4. 8.2.4 High Speed Differential Signal Routing Guidance
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 MMC Design Guidelines
      7. 8.2.7 Integrated Power Management Features
      8. 8.2.8 External Capacitors
        1. 8.2.8.1 LVCMOS External Capacitor Connections
      9. 8.2.9 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.5 Connections for Unused Pins

This section describes the Unused/Reserved balls connection requirements.

Note:

All power balls must be supplied with the voltages specified in Section 6.4, Recommended Operating Conditions, unless otherwise specified in Section 5.3, Signal Descriptions.

Table 5-77 Unused Balls Specific Connection Requirements
BALL NUMBER BALL NAME CONNECTION REQUIREMENTS
C22 OSC1_XI Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level if unused.
AE4 WKUP_LFOSC0_XI
AA3 TRSTn
K2 MCU_ADC0_REFN
K3 MCU_ADC0_REFP
V5 MCU_BYP_POR
H2 MCU_ADC1_REFP
H3 MCU_ADC1_REFN
K5 MCU_ADC0_AIN0
J3 MCU_ADC0_AIN1
J1 MCU_ADC0_AIN2
J5 MCU_ADC0_AIN3
K4 MCU_ADC0_AIN4
J4 MCU_ADC0_AIN5
J2 MCU_ADC0_AIN6
J6 MCU_ADC0_AIN7
F4 MCU_ADC1_AIN0
G6 MCU_ADC1_AIN1
G4 MCU_ADC1_AIN2
H5 MCU_ADC1_AIN3
F5 MCU_ADC1_AIN4
G5 MCU_ADC1_AIN5
G3 MCU_ADC1_AIN6
H4 MCU_ADC1_AIN7
F17 RESETz Each of these balls must be connected to the corresponding power supply through a separate external pull resistor to ensure these balls are held to a valid logic high level if unused.(1)
W4 MCU_RESETz
W5 MCU_PORz
E19 PORz
AA4 TCK
A21 TMS
AC7 WKUP_I2C0_SCL
AD6 WKUP_I2C0_SDA
AD7 MCU_I2C0_SDA
AD8 MCU_I2C0_SCL
F18 NMIn
C20 TDI
A20 TDO
AA1 EMU1
AA2 EMU0
F21 VPP_CORE This ball must be left unconnected if unused.
T6 VPP_MCU
AG5 SERDES0_REFCLKN
AG6 SERDES0_REFCLKP
AC9 SERDES0_REFRES
AH3 SERDES0_RXN
AG2 SERDES0_RXP
AH4 SERDES0_TXN
AG3 SERDES0_TXP
AH6 SERDES1_REFCLKN
AH7 SERDES1_REFCLKP
AC14 SERDES1_REFRES
AG9 SERDES1_RXN
AH10 SERDES1_RXP
AH9 SERDES1_TXN
AG8 SERDES1_TXP
(1) To determine which power supply is associated with any IO refer to Table 5-1, Pin Attributes.

Table 5-78 Reserved Balls Specific Connection Requirements
BALLS CONNECTION REQUIREMENTS
AA6 (RSV2), B1 (RSV3), AC23 (RSV4), C12 (RSV5), F9 (RSV6), F10 (RSV7), AD10 (RSV8), AC13 (RSV9), B28 (RSV10), A27 (RSV11), D23 (RSV12), E23 (RSV13), W6 (TEMP_DIODE_P), F16 (DDR_FS_RESETn), D24 (MMC0_CALPAD), F23 (MMC1_CALPAD) These balls must be left unconnected.
V4 (RSV1) These balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level.
Note:

All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled.

Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case where internal pull resistors are allowed as the only source/sink to hold a valid logic level.

Any balls connected to a via, test point, or PCB trace are considered used and must not depend on the internal pull resistor to hold a valid logic level.

Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This may be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be required to hold a valid logic level on balls with external connections.

If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state which could damage the IO cell.
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