米6体育平台手机版

ZHCSLA7C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

Tables and figures provided in this section define timing requirements and switching characteristics for clock signals.

Table 6-12 Clock Timing Requirements see Figure 6-12

NO.			MIN	MAX	UNIT
CLK1	t_{c(EXT_REFCLK1)}	Cycle time, EXT_REFCLK1	18.52		ns
CLK2	t_{w(EXT_REFCLK1H)}	Pulse Duration, EXT_REFCLK1 high	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK3	t_{w(EXT_REFCLK1L)}	Pulse Duration, EXT_REFCLK1 low	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK13	t_{c(MCU_EXT_REFCLK0)}	Cycle time, MCU_EXT_REFCLK0	18.52		ns
CLK14	t_{w(MCU_EXT_REFCLK0H)}	Pulse Duration, MCU_EXT_REFCLK0 high	F*0.45⁽²⁾	F*0.55⁽²⁾	ns
CLK15	t_{w(MCU_EXT_REFCLK0L)}	Pulse Duration, MCU_EXT_REFCLK0 low	F*0.45⁽²⁾	F*0.55⁽²⁾	ns

(1) E = EXT_REFCLK1 cycle time.

(2) F = MCU_EXT_REFCLK0 cycle time.

Figure 6-12 Clock Timing Requirements

Table 6-13 Clock Switching Characteristics see Figure 6-13

NO.	PARAMETER		MIN	MAX	UNIT
CLK4	t_{c(SYSCLKOUT0)}	Cycle time minimum,SYSCLKOUT0	6		ns
CLK5	t_{w(SYSCLKOUT0H)}	Pulse Duration minimum, SYSCLKOUT0 high	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK6	t_{w(SYSCLKOUT0L)}	Pulse Duration minimum, SYSCLKOUT0 low	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK7	t_c(OBSCLK0)	Cycle time minimum, OBSCLK0	5		ns
CLK8	t_w(OBSCLK0H)	Pulse Duration minimum, OBSCLK0 high	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK9	t_w(OBSCLK0L)	Pulse Duration minimum,OBSCLK0 low	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK10	t_c(CLKOUT0)	Cycle time minimum, MCU_CLKOUT0	20	40	ns
CLK11	t_w(CLKOUT0H)	Pulse Duration minimum, MCU_CLKOUT0 high	C*0.4⁽³⁾	C*0.6⁽³⁾	ns
CLK12	t_w(CLKOUT0L)	Pulse Duration minimum,MCU_CLKOUT0 low	C*0.4⁽³⁾	C*0.6⁽³⁾	ns
CLK16	t_{c(MCU_SYSCLKOUT0)}	Cycle time minimum,MCU_SYSCLKOUT0	6		ns
CLK17	t_{w(MCU_SYSCLKOUT0H)}	Pulse Duration minimum, MCU_SYSCLKOUT0 high	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK18	t_{w(MCU_SYSCLKOUT0L)}	Pulse Duration minimum, MCU_SYSCLKOUT0 low	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK19	t_{c(MCU_OBSCLK0)}	Cycle time minimum, MCU_OBSCLK0	5		ns
CLK20	t_{w(MCU_OBSCLK0H)}	Pulse Duration minimum, MCU_OBSCLK0 high	B*0.45⁽²⁾	B*0.55⁽²⁾	ns
CLK21	t_{w(MCU_OBSCLK0L)}	Pulse Duration minimum,MCU_OBSCLK0 low	B*0.45⁽²⁾	B*0.55⁽²⁾	ns

(1) A = SYSCLKOUT0 cycle time in MAIN domain; A = MCU_SYSCLKOUT0 in MCU domain.

(2) B = OBSCLK0 cycle time in MAIN domain; B = MCU_OBSCLK0 in MCU domain.

(3) C = MCU_CLKOUT0 cycle time.

Figure 6-13 Clock Switching Characteristics