米6体育平台手机版

ZHCSLA7C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

Table 6-26, Figure 6-30, and Figure 6-31 present timing requirements for LVDSRX interface.

Table 6-25 presents timing conditions for LVDSRX.

Table 6-25 LVDSRX Timing Conditions

PARAMETER		MODE	MIN	MAX	UNIT
INPUT CONDITIONS
SR_I	Input slew rate	1.8 V	1.3	2.64	V/ns
SR_I	Input slew rate	3.3 V	1.5	2.64	V/ns
PCB CONNECTIVITY REQUIREMENTS
t_{d(Trace Mismatch Delay)}	Propagation delay mismatch across all traces			50	ps

Table 6-26 Timing Requirements for LVDSRX

NO.	PARAMETER	DESCRIPTION	MIN	UNIT
V1	t_c(PCLK)	Cycle time, VIN0_PCLK	5.76^⁽¹⁾	ns
V2	t_w(PCLKH)	Pulse duration, VIN0_PCLK high	0.45 × P^⁽²⁾	ns
V3	t_w(PCLKL)	Pulse duration, VIN0_PCLK low	0.45 × P^⁽²⁾	ns
V4	t_{su(PCLK-CTL/DATA)}	Input setup time, control (VIN0_HD, VIN0_VD) and data (VIN0_DATA[15:0]) valid to VIN0_PCLK transition	2.42	ns
V5	t_{h(CTL/DAT-PCLK)}	Input hold time, VIN0_PCLK transition to control (VIN0_HD, VIN0_VD) valid	0.52	ns

(1) For maximum frequency of 165 MHz

(2) P = VIN0_PCLK period

Figure 6-30 LVDSRX Input Clock Signal

Figure 6-31 LVDSRX Input Timings