ZHCSLA7C December   2019  – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
    1. 3.1 功能方框图
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  CAL
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  CPSW2G
        1. 5.3.3.1 MCU Domain
      4. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 DDRSS Mapping
      5. 5.3.5  DMTIMER
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
      7. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
      8. 5.3.8  EHRPWM
        1. 5.3.8.1 MAIN Domain
      9. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
      10. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
        2. 5.3.10.2 WKUP Domain
      11. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 HyperBus
        1. 5.3.12.1 MCU Domain
      13. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
        2. 5.3.13.2 MCU Domain
        3. 5.3.13.3 WKUP Domain
      14. 5.3.14 MCAN
        1. 5.3.14.1 MCU Domain
      15. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
        2. 5.3.16.2 MCU Domain
      17. 5.3.17 MMCSD
        1. 5.3.17.1 MAIN Domain
      18. 5.3.18 CPTS
        1. 5.3.18.1 MCU Domain
        2. 5.3.18.2 MAIN Domain
      19. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 OSPI
        1. 5.3.20.1 MCU Domain
      21. 5.3.21 PRU_ICSSG
        1. 5.3.21.1 MAIN Domain
      22. 5.3.22 SERDES
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
        2. 5.3.23.2 MCU Domain
        3. 5.3.23.3 WKUP Domain
      24. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 Emulation and Debug
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 System and Miscellaneous
        1. 5.3.26.1 Boot Mode Configuration
          1. 5.3.26.1.1 MAIN Domain
          2. 5.3.26.1.2 MCU Domain
        2. 5.3.26.2 Clock
          1. 5.3.26.2.1 MAIN Domain
          2. 5.3.26.2.2 WKUP Domain
        3. 5.3.26.3 System
          1. 5.3.26.3.1 MAIN Domain
          2. 5.3.26.3.2 WKUP Domain
        4. 5.3.26.4 Miscellaneous
          1. 5.3.26.4.1 WKUP Domain
        5. 5.3.26.5 EFUSE
          1. 5.3.26.5.1 MAIN Domain
          2. 5.3.26.5.2 MCU Domain
      27. 5.3.27 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On Hours (POH)
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
      1. 6.5.1 Voltage and Core Clock Specifications
    6. 6.6 Electrical Characteristics
      1. 6.6.1 I2C OPEN DRAIN DC Electrical Characteristics
      2. 6.6.2 Analog OSC Buffers DC Electrical Characteristics
      3. 6.6.3 Analog ADC DC Electrical Characteristics
      4. 6.6.4 DPHY CSI2 Buffers DC Electrical Characteristics
      5. 6.6.5 OLDI LVDS Buffers DC Electrical Characteristics
        1. 6.6.5.1 LVCMOS Buffers DC Electrical Characteristics
      6. 6.6.6 USBHS Buffers DC Electrical Characteristics
      7. 6.6.7 SERDES Buffers DC Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement
        3. 6.9.2.3 Power-Up Sequencing
        4. 6.9.2.4 Power-Down Sequencing
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Electrical Data/Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source
          8. 6.9.4.1.8 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 6.9.4.5 Module and Peripheral Clock Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  VIN
        2. 6.9.5.2  CPSW2G
          1. 6.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.2.2 CPSW2G RMII Timings
            1. 6.9.5.2.2.1 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. 6.9.5.2.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. 6.9.5.2.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 6.9.5.2.3 CPSW2G RGMII Timings
            1. 6.9.5.2.3.1 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. 6.9.5.2.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. 6.9.5.2.3.3 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. 6.9.5.2.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode
        3. 6.9.5.3  CSI2
        4. 6.9.5.4  DDRSS
        5. 6.9.5.5  DSS
        6. 6.9.5.6  eCAP
          1. 6.9.5.6.1 eCAP Timing Requirements
          2. 6.9.5.6.2 eCAP Switching Characteristics
        7. 6.9.5.7  ePWM
          1. 6.9.5.7.1 ePWM Timing Requirements
          2. 6.9.5.7.2 ePWM Switching Characteristics
        8. 6.9.5.8  eQEP
          1. 6.9.5.8.1 eQEP Timing Requirements
          2. 6.9.5.8.2 eQEP Switching Characteristics
        9. 6.9.5.9  GPIO
          1. 6.9.5.9.1 GPIO Timing Requirements
          2. 6.9.5.9.2 GPIO Switching Characteristics
        10. 6.9.5.10 GPMC
          1. 6.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. 6.9.5.10.1.1 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. 6.9.5.10.1.2 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 6.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. 6.9.5.10.2.1 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.2.2 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 6.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. 6.9.5.10.3.1 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.3.2 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 6.9.5.11 HyperBus
          1. 6.9.5.11.1 Timing Requirements for HyperBus Initialization
          2. 6.9.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.9.5.12 I2C
        13. 6.9.5.13 MCAN
        14. 6.9.5.14 MCASP
          1. 6.9.5.14.1 MCASP Timing Requirements and Switching Characteristics
        15. 6.9.5.15 MCSPI
          1. 6.9.5.15.1 SPI—Master Mode
          2. 6.9.5.15.2 SPI—Slave Mode
        16. 6.9.5.16 MMCSD
          1. 6.9.5.16.1 MMCSDi — eMMC/SD/SDIO Card Interface
            1. 6.9.5.16.1.1 Default Speed, 3.3V Legacy SDR Mode
            2. 6.9.5.16.1.2 High Speed, 3.3V High Speed SDR Mode
            3. 6.9.5.16.1.3 UHS-I SDR12, 1.8-V Legacy SDR Mode
            4. 6.9.5.16.1.4 UHS-I SDR25 Mode
            5. 6.9.5.16.1.5 UHS-I DDR50 Mode
            6. 6.9.5.16.1.6 UHS-I SDR50 Mode
            7. 6.9.5.16.1.7 UHS-I SDR104 / HS200 Mode
        17. 6.9.5.17 CPTS
          1. 6.9.5.17.1 CPTS Timing Requirements
          2. 6.9.5.17.2 CPTS Switching Characteristics
        18. 6.9.5.18 OSPI
          1. 6.9.5.18.1 OSPI with Data Training
            1. 6.9.5.18.1.1 OSPI Switching Characteristics - Data Training
          2. 6.9.5.18.2 OSPI without Data Training
            1. 6.9.5.18.2.1 OSPI Timing Requirements - SDR Mode
            2. 6.9.5.18.2.2 OSPI Switching Characteristics - SDR Mode
            3. 6.9.5.18.2.3 OSPI Timing Requirements - DDR Mode
            4. 6.9.5.18.2.4 OSPI Switching Characteristics - DDR Mode
        19. 6.9.5.19 OLDI
          1. 6.9.5.19.1 OLDI Switching Characteristics
        20. 6.9.5.20 PCIE
        21. 6.9.5.21 PRU_ICSSG
          1. 6.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 6.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. 6.9.5.21.1.1.1 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 6.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. 6.9.5.21.1.2.1 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 6.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. 6.9.5.21.1.3.1 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. 6.9.5.21.1.3.2 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 6.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. 6.9.5.21.1.4.1 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. 6.9.5.21.1.4.2 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. 6.9.5.21.1.4.3 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 6.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. 6.9.5.21.2.1.1 PRU_ICSSG PWM Switching Characteristics
          3. 6.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 6.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. 6.9.5.21.3.1.1 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. 6.9.5.21.3.1.2 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. 6.9.5.21.3.1.3 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 6.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 6.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. 6.9.5.21.4.1.1 PRU_ICSSG UART Timing Requirements
              2. 6.9.5.21.4.1.2 PRU_ICSSG UART Switching Characteristics
          5. 6.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 6.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. 6.9.5.21.5.1.1 PRU_ICSSG ECAP Timing Requirements
              2. 6.9.5.21.5.1.2 PRU_ICSSG ECAP Switching Characteristics
          6. 6.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. 6.9.5.21.6.1.1 PRU_ICSSG MDIO Timing Requirements
              2. 6.9.5.21.6.1.2 PRU_ICSSG MDIO Switching Characteristics - MDIO_CLK
              3. 6.9.5.21.6.1.3 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 6.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. 6.9.5.21.6.2.1 PRU_ICSSG RGMII Timing Requirements - RGMII_RXC
              2. 6.9.5.21.6.2.2 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RX_CTL
              3. 6.9.5.21.6.2.3 PRU_ICSSG RGMII Switching Characteristics - RGMII_TXC
              4. 6.9.5.21.6.2.4 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL
            3. 6.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. 6.9.5.21.6.3.1 PRU_ICSSG MII_RT Timing Requirements – MII_RX_CLK
              2. 6.9.5.21.6.3.2 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RX_DV, and MII_RX_ER
              3. 6.9.5.21.6.3.3 PRU_ICSSG MII_RT Switching Characteristics – MII_TX_CLK
              4. 6.9.5.21.6.3.4 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 6.9.5.22 Timers
          1. 6.9.5.22.1 Timing Requirements for Timers
          2. 6.9.5.22.2 Switching Characteristics for Timers
        23. 6.9.5.23 UART
          1. 6.9.5.23.1 Timing Requirements for UART
          2. 6.9.5.23.2 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 6.9.5.24 USB
        25. 6.9.5.25 Emulation and Debug
          1. 6.9.5.25.1 Debug Trace
          2. 6.9.5.25.2 JTAG
            1. 6.9.5.25.2.1 JTAG Electrical Data and Timing
              1. 6.9.5.25.2.1.1 JTAG Timing Requirements
              2. 6.9.5.25.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53
      2. 7.2.2 Arm Cortex-R5F
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 PRU_ICSSG
        1. 7.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores
        2. 7.3.1.2 PRU_ICSSG Broadside Accelerators Overview
        3. 7.3.1.3 PRU_ICSSG UART Module
        4. 7.3.1.4 PRU_ICSSG ECAP Module
        5. 7.3.1.5 PRU_ICSSG PWM Module
        6. 7.3.1.6 PRU_ICSSG MII_G_RT Module
        7. 7.3.1.7 PRU_ICSSG MII MDIO Module
        8. 7.3.1.8 PRU_ICSSG IEP
      2. 7.3.2 GPU
    4. 7.4 Other Subsystems
      1. 7.4.1 DMSC
      2. 7.4.2 MSMC
      3. 7.4.3 NAVSS
        1. 7.4.3.1 NAVSS0
        2. 7.4.3.2 MCU_NAVSS0
      4. 7.4.4 PDMA Controller
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  CAL
        3. 7.4.5.3  CPSW2G
        4. 7.4.5.4  DCC
        5. 7.4.5.5  DDRSS
        6. 7.4.5.6  DSS
        7. 7.4.5.7  ЕCAP
        8. 7.4.5.8  EPWM
        9. 7.4.5.9  ELM
        10. 7.4.5.10 ESM
        11. 7.4.5.11 EQEP
        12. 7.4.5.12 GPIO
        13. 7.4.5.13 GPMC
        14. 7.4.5.14 HyperBus
        15. 7.4.5.15 I2C
        16. 7.4.5.16 MCAN
        17. 7.4.5.17 MCASP
        18. 7.4.5.18 MCRC
        19. 7.4.5.19 MCSPI
        20. 7.4.5.20 MMCSD
        21. 7.4.5.21 OSPI
        22. 7.4.5.22 PCIE
        23. 7.4.5.23 SerDes
        24. 7.4.5.24 RTI
        25. 7.4.5.25 Timers
        26. 7.4.5.26 UART
        27. 7.4.5.27 USB
    5. 7.5 Identification
      1. 7.5.1 Revision Identification
      2. 7.5.2 Die Identification
      3. 7.5.3 JTAG Identification
      4. 7.5.4 ROM Code Identification
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG and EMU
      4. 8.1.4 Reset
      5. 8.1.5 Unused Pins
      6. 8.1.6 Hardware Design Guide for AM65x/DRA80xM Devices
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (Only Available in Octal Flash Devices)
      3. 8.2.3 USB Design Guidelines
      4. 8.2.4 High Speed Differential Signal Routing Guidance
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 MMC Design Guidelines
      7. 8.2.7 Integrated Power Management Features
      8. 8.2.8 External Capacitors
        1. 8.2.8.1 LVCMOS External Capacitor Connections
      9. 8.2.9 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.4 Pin Multiplexing

Table 5-76 describes the device pin multiplexing associated with pins.

Note:

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions.

Table 5-76, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see section Pad Configuration Registers in the device TRM. Refer to the respective peripheral chapter in the device TRM for information associated with peripheral signal multiplexing.

Note:

When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.

Note:

Table 5-76, Pin Multiplexing does not include SerDes signal functions. For more information, see section Serializer/Deserializer (SerDes) in the device TRM.

Note:

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.

For more information on the I/O cell configurations, see section Pad Configuration Registers in the device TRM.

Table 5-76 Pin Multiplexing
ADDRESSREGISTER NAMEBALL NUMBERMUXMODE[7:0] SETTINGS
01234567Bootstrap
0x0011C000CTRLMMR_PADCONFIG0 M27GPMC0_AD0VOUT1_DATA0VIN0_DATA12GPIO0_0BOOTMODE00
0x0011C004CTRLMMR_PADCONFIG1 M23GPMC0_AD1VOUT1_DATA1VIN0_DATA13GPIO0_1BOOTMODE01
0x0011C008CTRLMMR_PADCONFIG2 M28GPMC0_AD2VOUT1_DATA2VIN0_DATA14GPIO0_2BOOTMODE02
0x0011C00CCTRLMMR_PADCONFIG3 M24GPMC0_AD3VOUT1_DATA3VIN0_DATA15GPIO0_3BOOTMODE03
0x0011C010CTRLMMR_PADCONFIG4 N24GPMC0_AD4VOUT1_DATA4GPIO0_4BOOTMODE04
0x0011C014CTRLMMR_PADCONFIG5 N27GPMC0_AD5VOUT1_DATA5GPIO0_5BOOTMODE05
0x0011C018CTRLMMR_PADCONFIG6 N28GPMC0_AD6VOUT1_DATA6GPIO0_6BOOTMODE06
0x0011C01CCTRLMMR_PADCONFIG7 M25GPMC0_AD7VOUT1_DATA7GPIO0_7BOOTMODE07
0x0011C020CTRLMMR_PADCONFIG8 N23GPMC0_AD8VOUT1_DATA8VIN0_DATA0PRG2_PRU0_GPO12PRG2_PRU0_GPI12PRG2_PWM2_A0GPIO0_8BOOTMODE08
0x0011C024CTRLMMR_PADCONFIG9 M26GPMC0_AD9VOUT1_DATA9VIN0_DATA1PRG2_PRU0_GPO13PRG2_PRU0_GPI13PRG2_PWM2_B0GPIO0_9BOOTMODE09
0x0011C028CTRLMMR_PADCONFIG10 P28GPMC0_AD10VOUT1_DATA10VIN0_DATA2PRG2_PRU0_GPO14PRG2_PRU0_GPI14PRG2_PWM0_TZ_INGPIO0_10BOOTMODE10
0x0011C02CCTRLMMR_PADCONFIG11 P27GPMC0_AD11VOUT1_DATA11VIN0_DATA3PRG2_PRU0_GPO15PRG2_PRU0_GPI15PRG2_PWM2_A1GPIO0_11BOOTMODE11
0x0011C030CTRLMMR_PADCONFIG12 N26GPMC0_AD12VOUT1_DATA12VIN0_DATA4PRG2_PRU1_GPO12PRG2_PRU1_GPI12PRG2_PWM2_B1GPIO0_12BOOTMODE12
0x0011C034CTRLMMR_PADCONFIG13 N25GPMC0_AD13VOUT1_DATA13VIN0_DATA5PRG2_PRU1_GPO13PRG2_PRU1_GPI13PRG2_PWM2_A2GPIO0_13BOOTMODE13
0x0011C038CTRLMMR_PADCONFIG14 P24GPMC0_AD14VOUT1_DATA14VIN0_DATA6PRG2_PRU1_GPO14PRG2_PRU1_GPI14PRG2_PWM0_TZ_OUTGPIO0_14BOOTMODE14
0x0011C03CCTRLMMR_PADCONFIG15 R27GPMC0_AD15VOUT1_DATA15VIN0_DATA7PRG2_PRU1_GPO15PRG2_PRU1_GPI15PRG2_PWM2_B2GPIO0_15BOOTMODE15
0x0011C040CTRLMMR_PADCONFIG16 R28GPMC0_CLKVOUT1_DATA16VIN0_PCLKGPMC0_FCLK_MUXGPIO0_16
0x0011C044CTRLMMR_PADCONFIG17 P25GPMC0_ADVn_ALEVOUT1_DATA17GPIO0_17BOOTMODE16
0x0011C048CTRLMMR_PADCONFIG18 P26GPMC0_OEn_REnVOUT1_DATA18GPIO0_18BOOTMODE17
0x0011C04CCTRLMMR_PADCONFIG19 U28GPMC0_WEnVOUT1_DATA19GPIO0_19BOOTMODE18
0x0011C050CTRLMMR_PADCONFIG20 T28GPMC0_BE0n_CLEVOUT1_DATA20GPIO0_20
0x0011C054CTRLMMR_PADCONFIG21 P23GPMC0_BE1nVOUT1_DATA21VIN0_HDPRG2_PRU0_GPO17PRG2_PRU0_GPI17TIMER_IO2PRG2_PWM2_TZ_INGPIO0_21
0x0011C058CTRLMMR_PADCONFIG22 R26GPMC0_WAIT0VOUT1_DATA22GPIO0_22
0x0011C05CCTRLMMR_PADCONFIG23 R23GPMC0_WAIT1VOUT1_DATA23VIN0_VDPRG2_PWM1_A0PRG2_IEP1_EDC_LATCH_IN0TIMER_IO3PRG2_IEP0_EDIO_DATA_IN_OUT28GPIO0_23
0x0011C060CTRLMMR_PADCONFIG24 T25GPMC0_WPnVOUT1_VSYNCGPIO0_24
0x0011C064CTRLMMR_PADCONFIG25 T24GPMC0_DIRVOUT1_HSYNCVIN0_DATA8PRG2_PWM1_B0PRG2_IEP1_EDC_SYNC_OUT0TIMER_IO6PRG2_IEP0_EDIO_DATA_IN_OUT29GPIO0_25
0x0011C068CTRLMMR_PADCONFIG26 R24GPMC0_CSn0VOUT1_PCLKGPIO0_26
0x0011C06CCTRLMMR_PADCONFIG27 T23GPMC0_CSn1VOUT1_DEVIN0_DATA9PRG2_PRU1_GPO17PRG2_PRU1_GPI17TIMER_IO7PRG2_PWM2_TZ_OUTGPIO0_27
0x0011C070CTRLMMR_PADCONFIG28 R25GPMC0_CSn2VOUT1_EXTPCLKINVIN0_DATA10GPMC0_A27PRG2_IEP1_EDC_LATCH_IN1I2C2_SDAPRG2_IEP0_EDIO_DATA_IN_OUT30GPIO0_28
0x0011C074CTRLMMR_PADCONFIG29 T27GPMC0_CSn3VIN0_DATA11GPMC0_A26PRG2_IEP1_EDC_SYNC_OUT1I2C2_SCLPRG2_IEP0_EDIO_DATA_IN_OUT31GPIO0_29
0x0011C078CTRLMMR_PADCONFIG30 AF18PRG2_PRU0_GPO0PRG2_PRU0_GPI0PRG2_RGMII1_RD0GPMC0_A25TRC_CLKEHRPWM0_SYNCIPRG2_PWM3_A0GPIO0_30
0x0011C07CCTRLMMR_PADCONFIG31 AE18PRG2_PRU0_GPO1PRG2_PRU0_GPI1PRG2_RGMII1_RD1GPMC0_A24TRC_CTLEHRPWM0_SYNCOSYNC2_OUTGPIO0_31
0x0011C080CTRLMMR_PADCONFIG32 AH17PRG2_PRU0_GPO2PRG2_PRU0_GPI2PRG2_RGMII1_RD2GPMC0_A23TRC_DATA0EHRPWM_TZn_IN0SYNC3_OUTGPIO0_32
0x0011C084CTRLMMR_PADCONFIG33 AG18PRG2_PRU0_GPO3PRG2_PRU0_GPI3PRG2_RGMII1_RD3GPMC0_A22TRC_DATA1EHRPWM0_APRG2_PWM3_B0GPIO0_33
0x0011C088CTRLMMR_PADCONFIG34 AG17PRG2_PRU0_GPO4PRG2_PRU0_GPI4PRG2_RGMII1_RX_CTLGPMC0_A21TRC_DATA2EHRPWM0_BPRG2_PWM0_A0GPIO0_34
0x0011C08CCTRLMMR_PADCONFIG35 AF17PRG2_PRU0_GPO5PRG2_PRU0_GPI5PRG2_RGMII1_RXCGPMC0_A20TRC_DATA3EHRPWM1_APRG2_PWM3_A1GPIO0_35
0x0011C090CTRLMMR_PADCONFIG36 AE17PRG2_PRU0_GPO6PRG2_PRU0_GPI6PRG2_RGMII1_TX_CTLGPMC0_A19TRC_DATA4EHRPWM1_BPRG2_PWM3_B1GPIO0_36
0x0011C094CTRLMMR_PADCONFIG37 AC19PRG2_PRU0_GPO7PRG2_PRU0_GPI7PRG2_MDIO0_MDIOGPMC0_A18TRC_DATA5EHRPWM_TZn_IN1EHRPWM_SOCAGPIO0_37
0x0011C098CTRLMMR_PADCONFIG38 AH16PRG2_PRU0_GPO8PRG2_PRU0_GPI8PRG2_RGMII1_TD0GPMC0_A17TRC_DATA6EHRPWM2_APRG2_PWM0_B0GPIO0_38
0x0011C09CCTRLMMR_PADCONFIG39 AG16PRG2_PRU0_GPO9PRG2_PRU0_GPI9PRG2_RGMII1_TD1GPMC0_A16TRC_DATA7EHRPWM2_BGPIO0_39
0x0011C0A0CTRLMMR_PADCONFIG40 AF16PRG2_PRU0_GPO10PRG2_PRU0_GPI10PRG2_RGMII1_TD2GPMC0_A15TRC_DATA8EHRPWM_TZn_IN2EHRPWM_SOCBGPIO0_40
0x0011C0A4CTRLMMR_PADCONFIG41 AE16PRG2_PRU0_GPO11PRG2_PRU0_GPI11PRG2_RGMII1_TD3GPMC0_A14TRC_DATA9PRG2_ECAP0_IN_APWM_OUTGPIO0_41
0x0011C0A8CTRLMMR_PADCONFIG42 AD16PRG2_PRU0_GPO16PRG2_PRU0_GPI16PRG2_RGMII1_TXCGPMC0_A13TRC_DATA10PRG2_PWM0_A1GPIO0_42
0x0011C0ACCTRLMMR_PADCONFIG43 AH15PRG2_PRU1_GPO0PRG2_PRU1_GPI0PRG2_RGMII2_RD0GPMC0_A12TRC_DATA11EHRPWM3_APRG2_PWM3_A2GPIO0_43
0x0011C0B0CTRLMMR_PADCONFIG44 AC16PRG2_PRU1_GPO1PRG2_PRU1_GPI1PRG2_RGMII2_RD1GPMC0_A11TRC_DATA12EHRPWM3_BPRG2_PWM3_B2GPIO0_44
0x0011C0B4CTRLMMR_PADCONFIG45 AD17PRG2_PRU1_GPO2PRG2_PRU1_GPI2PRG2_RGMII2_RD2GPMC0_A10TRC_DATA13EHRPWM3_SYNCIPRG2_PWM0_B1GPIO0_45
0x0011C0B8CTRLMMR_PADCONFIG46 AH14PRG2_PRU1_GPO3PRG2_PRU1_GPI3PRG2_RGMII2_RD3GPMC0_A9TRC_DATA14EHRPWM3_SYNCOGPIO0_46
0x0011C0BCCTRLMMR_PADCONFIG47 AG14PRG2_PRU1_GPO4PRG2_PRU1_GPI4PRG2_RGMII2_RX_CTLGPMC0_A8TRC_DATA15EHRPWM_TZn_IN3PRG2_ECAP0_SYNC_OUTGPIO0_47
0x0011C0C0CTRLMMR_PADCONFIG48 AG15PRG2_PRU1_GPO5PRG2_PRU1_GPI5PRG2_RGMII2_RXCGPMC0_A7TRC_DATA16EHRPWM4_AGPIO0_48
0x0011C0C4CTRLMMR_PADCONFIG49 AC17PRG2_PRU1_GPO6PRG2_PRU1_GPI6PRG2_RGMII2_TX_CTLGPMC0_A6TRC_DATA17EHRPWM4_BGPIO0_49
0x0011C0C8CTRLMMR_PADCONFIG50 AE15PRG2_PRU1_GPO7PRG2_PRU1_GPI7PRG2_MDIO0_MDCGPMC0_A5TRC_DATA18EHRPWM_TZn_IN4PRG2_PWM3_TZ_INGPIO0_50
0x0011C0CCCTRLMMR_PADCONFIG51 AD15PRG2_PRU1_GPO8PRG2_PRU1_GPI8PRG2_RGMII2_TD0GPMC0_A4TRC_DATA19EHRPWM5_APRG2_PWM0_A2GPIO0_51
0x0011C0D0CTRLMMR_PADCONFIG52 AF14PRG2_PRU1_GPO9PRG2_PRU1_GPI9PRG2_RGMII2_TD1GPMC0_A3TRC_DATA20EHRPWM5_BPRG2_PWM3_TZ_OUTGPIO0_52
0x0011C0D4CTRLMMR_PADCONFIG53 AC15PRG2_PRU1_GPO10PRG2_PRU1_GPI10PRG2_RGMII2_TD2GPMC0_A2TRC_DATA21EHRPWM_TZn_IN5PRG2_PWM0_B2GPIO0_53
0x0011C0D8CTRLMMR_PADCONFIG54 AD14PRG2_PRU1_GPO11PRG2_PRU1_GPI11PRG2_RGMII2_TD3GPMC0_A1TRC_DATA22PRG2_ECAP0_SYNC_INGPIO0_54
0x0011C0DCCTRLMMR_PADCONFIG55 AE14PRG2_PRU1_GPO16PRG2_PRU1_GPI16PRG2_RGMII2_TXCGPMC0_A0TRC_DATA23PRG2_PWM1_TZ_OUTGPIO0_55
0x0011C0E0CTRLMMR_PADCONFIG56 AE22PRG1_PRU0_GPO0PRG1_PRU0_GPI0PRG1_RGMII1_RD0PRG1_PWM3_A0GPIO0_56
0x0011C0E4CTRLMMR_PADCONFIG57 AG24PRG1_PRU0_GPO1PRG1_PRU0_GPI1PRG1_RGMII1_RD1PRG1_PWM3_B0GPIO0_57
0x0011C0E8CTRLMMR_PADCONFIG58 AF23PRG1_PRU0_GPO2PRG1_PRU0_GPI2PRG1_RGMII1_RD2PRG1_PWM2_A0GPIO0_58
0x0011C0ECCTRLMMR_PADCONFIG59 AD21PRG1_PRU0_GPO3PRG1_PRU0_GPI3PRG1_RGMII1_RD3PRG1_PWM3_A2GPIO0_59
0x0011C0F0CTRLMMR_PADCONFIG60 AG23PRG1_PRU0_GPO4PRG1_PRU0_GPI4PRG1_RGMII1_RX_CTLPRG1_PWM2_B0GPIO0_60
0x0011C0F4CTRLMMR_PADCONFIG61 AF27PRG1_PRU0_GPO5PRG1_PRU0_GPI5PRG1_PWM3_B2GPIO0_61
0x0011C0F8CTRLMMR_PADCONFIG62 AF22PRG1_PRU0_GPO6PRG1_PRU0_GPI6PRG1_RGMII1_RXCPRG1_PWM3_A1GPIO0_62
0x0011C0FCCTRLMMR_PADCONFIG63 AG27PRG1_PRU0_GPO7PRG1_PRU0_GPI7PRG1_IEP0_EDC_LATCH_IN1PRG1_PWM3_B1GPIO0_63
0x0011C100CTRLMMR_PADCONFIG64 AF28PRG1_PRU0_GPO8PRG1_PRU0_GPI8PRG1_PWM2_A1GPIO0_64
0x0011C104CTRLMMR_PADCONFIG65 AF26PRG1_PRU0_GPO9PRG1_PRU0_GPI9PRG1_UART0_CTSnPRG1_PWM3_TZ_INSPI2_CS1PRG1_IEP0_EDIO_DATA_IN_OUT28GPIO0_65
0x0011C108CTRLMMR_PADCONFIG66 AH25PRG1_PRU0_GPO10PRG1_PRU0_GPI10PRG1_UART0_RTSnPRG1_PWM2_B1SPI2_CS2PRG1_IEP0_EDIO_DATA_IN_OUT29GPIO0_66
0x0011C10CCTRLMMR_PADCONFIG67 AF21PRG1_PRU0_GPO11PRG1_PRU0_GPI11PRG1_RGMII1_TX_CTLPRG1_PWM3_TZ_OUTPRG1_PRU0_GPO15GPIO0_67
0x0011C110CTRLMMR_PADCONFIG68 AH20PRG1_PRU0_GPO12PRG1_PRU0_GPI12PRG1_RGMII1_TD0PRG1_PWM0_A0PRG1_PRU0_GPO11GPIO0_68
0x0011C114CTRLMMR_PADCONFIG69 AH21PRG1_PRU0_GPO13PRG1_PRU0_GPI13PRG1_RGMII1_TD1PRG1_PWM0_B0PRG1_PRU0_GPO12GPIO0_69
0x0011C118CTRLMMR_PADCONFIG70 AG20PRG1_PRU0_GPO14PRG1_PRU0_GPI14PRG1_RGMII1_TD2PRG1_PWM0_A1PRG1_PRU0_GPO13GPIO0_70
0x0011C11CCTRLMMR_PADCONFIG71 AD19PRG1_PRU0_GPO15PRG1_PRU0_GPI15PRG1_RGMII1_TD3PRG1_PWM0_B1PRG1_PRU0_GPO14GPIO0_71
0x0011C120CTRLMMR_PADCONFIG72 AD20PRG1_PRU0_GPO16PRG1_PRU0_GPI16PRG1_RGMII1_TXCPRG1_PWM0_A2GPIO0_72
0x0011C124CTRLMMR_PADCONFIG73 AH26PRG1_PRU0_GPO17PRG1_PRU0_GPI17PRG1_IEP0_EDC_SYNC_OUT1PRG1_PWM0_B2GPIO0_73
0x0011C128CTRLMMR_PADCONFIG74 AG25PRG1_PRU0_GPO18PRG1_PRU0_GPI18PRG1_IEP0_EDC_LATCH_IN0PRG1_PWM0_TZ_INGPIO0_74
0x0011C12CCTRLMMR_PADCONFIG75 AG26PRG1_PRU0_GPO19PRG1_PRU0_GPI19PRG1_IEP0_EDC_SYNC_OUT0PRG1_PWM0_TZ_OUTGPIO0_75
0x0011C130CTRLMMR_PADCONFIG76 AH24PRG1_PRU1_GPO0PRG1_PRU1_GPI0PRG1_RGMII2_RD0GPIO0_76
0x0011C134CTRLMMR_PADCONFIG77 AH23PRG1_PRU1_GPO1PRG1_PRU1_GPI1PRG1_RGMII2_RD1GPIO0_77
0x0011C138CTRLMMR_PADCONFIG78 AG21PRG1_PRU1_GPO2PRG1_PRU1_GPI2PRG1_RGMII2_RD2PRG1_PWM2_A2GPIO0_78
0x0011C13CCTRLMMR_PADCONFIG79 AH22PRG1_PRU1_GPO3PRG1_PRU1_GPI3PRG1_RGMII2_RD3EQEP1_AGPIO0_79
0x0011C140CTRLMMR_PADCONFIG80 AE21PRG1_PRU1_GPO4PRG1_PRU1_GPI4PRG1_RGMII2_RX_CTLPRG1_PWM2_B2EQEP1_BGPIO0_80
0x0011C144CTRLMMR_PADCONFIG81 AC22PRG1_PRU1_GPO5PRG1_PRU1_GPI5EQEP1_SGPIO0_81
0x0011C148CTRLMMR_PADCONFIG82 AG22PRG1_PRU1_GPO6PRG1_PRU1_GPI6PRG1_RGMII2_RXCGPIO0_82
0x0011C14CCTRLMMR_PADCONFIG83 AD23PRG1_PRU1_GPO7PRG1_PRU1_GPI7PRG1_IEP1_EDC_LATCH_IN1SPI2_CS0UART1_TXDGPIO0_83
0x0011C150CTRLMMR_PADCONFIG84 AE24PRG1_PRU1_GPO8PRG1_PRU1_GPI8PRG1_PWM2_TZ_OUTGPIO0_84
0x0011C154CTRLMMR_PADCONFIG85 AF25PRG1_PRU1_GPO9PRG1_PRU1_GPI9PRG1_UART0_RXDPRG1_IEP0_EDIO_DATA_IN_OUT30GPIO0_85
0x0011C158CTRLMMR_PADCONFIG86 AF24PRG1_PRU1_GPO10PRG1_PRU1_GPI10PRG1_UART0_TXDPRG1_PWM2_TZ_INSPI2_CS3PRG1_IEP0_EDIO_DATA_IN_OUT31GPIO0_86
0x0011C15CCTRLMMR_PADCONFIG87 AC20PRG1_PRU1_GPO11PRG1_PRU1_GPI11PRG1_RGMII2_TX_CTLEQEP1_IPRG1_PRU1_GPO15GPIO0_87
0x0011C160CTRLMMR_PADCONFIG88 AE20PRG1_PRU1_GPO12PRG1_PRU1_GPI12PRG1_RGMII2_TD0PRG1_PWM1_A0PRG1_PRU1_GPO11GPIO0_88
0x0011C164CTRLMMR_PADCONFIG89 AF19PRG1_PRU1_GPO13PRG1_PRU1_GPI13PRG1_RGMII2_TD1PRG1_PWM1_B0PRG1_PRU1_GPO12GPIO0_89
0x0011C168CTRLMMR_PADCONFIG90 AH19PRG1_PRU1_GPO14PRG1_PRU1_GPI14PRG1_RGMII2_TD2PRG1_PWM1_A1PRG1_PRU1_GPO13GPIO0_90
0x0011C16CCTRLMMR_PADCONFIG91 AG19PRG1_PRU1_GPO15PRG1_PRU1_GPI15PRG1_RGMII2_TD3PRG1_PWM1_B1PRG1_PRU1_GPO14GPIO0_91
0x0011C170CTRLMMR_PADCONFIG92 AE19PRG1_PRU1_GPO16PRG1_PRU1_GPI16PRG1_RGMII2_TXCPRG1_PWM1_A2GPIO0_92
0x0011C174CTRLMMR_PADCONFIG93 AE23PRG1_PRU1_GPO17PRG1_PRU1_GPI17PRG1_IEP1_EDC_SYNC_OUT1PRG1_PWM1_B2SPI2_CLKPRG1_ECAP0_SYNC_OUTUART1_RXDGPIO0_93
0x0011C178CTRLMMR_PADCONFIG94 AD22PRG1_PRU1_GPO18PRG1_PRU1_GPI18PRG1_IEP1_EDC_LATCH_IN0PRG1_PWM1_TZ_INSPI2_D0PRG1_ECAP0_SYNC_INUART1_CTSnGPIO0_94
0x0011C17CCTRLMMR_PADCONFIG95 AC21PRG1_PRU1_GPO19PRG1_PRU1_GPI19PRG1_IEP1_EDC_SYNC_OUT0PRG1_PWM1_TZ_OUTSPI2_D1PRG1_ECAP0_IN_APWM_OUTUART1_RTSnGPIO0_95
0x0011C180CTRLMMR_PADCONFIG96 AD18PRG1_MDIO0_MDIOSPI1_CS2PRG2_PWM1_A1GPIO1_0
0x0011C184CTRLMMR_PADCONFIG97 AH18PRG1_MDIO0_MDCSPI1_CS3PRG2_PWM1_B1GPIO1_1
0x0011C188CTRLMMR_PADCONFIG98 D25MMC0_DAT7UART0_DCDnEQEP2_AGPIO1_2
0x0011C18CCTRLMMR_PADCONFIG99 B26MMC0_DAT6UART0_DSRnEQEP2_BGPIO1_3
0x0011C190CTRLMMR_PADCONFIG100 A24MMC0_DAT5UART0_DTRnEQEP2_IGPIO1_4
0x0011C194CTRLMMR_PADCONFIG101 E24MMC0_DAT4UART0_RINEQEP2_SGPIO1_5
0x0011C198CTRLMMR_PADCONFIG102 A25MMC0_DAT3GPIO1_6
0x0011C19CCTRLMMR_PADCONFIG103 C26MMC0_DAT2GPIO1_7
0x0011C1A0CTRLMMR_PADCONFIG104 E25MMC0_DAT1GPIO1_8
0x0011C1A4CTRLMMR_PADCONFIG105 A26MMC0_DAT0GPIO1_9
0x0011C1A8CTRLMMR_PADCONFIG106 B25MMC0_CLKGPIO1_10
0x0011C1ACCTRLMMR_PADCONFIG107 B27MMC0_CMDGPIO1_11
0x0011C1B0CTRLMMR_PADCONFIG108 C25MMC0_DSGPIO1_12
0x0011C1B4CTRLMMR_PADCONFIG109 A23MMC0_SDCDPRG2_IEP0_EDIO_OUTVALIDGPIO1_13
0x0011C1B8CTRLMMR_PADCONFIG110 B23MMC0_SDWPGPIO1_14
0x0011C1BCCTRLMMR_PADCONFIG111 AG13SPI0_CS0GPIO1_15
0x0011C1C0CTRLMMR_PADCONFIG112 AF13SPI0_CS1CPTS0_TS_COMPI2C3_SCLPRG1_IEP0_EDIO_OUTVALIDGPIO1_16
0x0011C1C4CTRLMMR_PADCONFIG113 AH13SPI0_CLKGPIO1_17
0x0011C1C8CTRLMMR_PADCONFIG114 AE13SPI0_D0GPIO1_18
0x0011C1CCCTRLMMR_PADCONFIG115 AD13SPI0_D1GPIO1_19
0x0011C1D0CTRLMMR_PADCONFIG116 AD12SPI1_CS0PRG2_IEP0_EDC_LATCH_IN0PRG2_UART0_CTSnPRG0_IEP0_EDIO_OUTVALIDGPIO1_20
0x0011C1D4CTRLMMR_PADCONFIG117 AG12SPI1_CS1CPTS0_TS_SYNCI2C3_SDAGPIO1_21
0x0011C1D8CTRLMMR_PADCONFIG118 AH12SPI1_CLKPRG2_IEP0_EDC_SYNC_OUT0PRG2_UART0_RTSnGPIO1_22
0x0011C1DCCTRLMMR_PADCONFIG119 AE12SPI1_D0PRG2_IEP0_EDC_LATCH_IN1PRG2_UART0_RXDGPIO1_23
0x0011C1E0CTRLMMR_PADCONFIG120 AF12SPI1_D1PRG2_IEP0_EDC_SYNC_OUT1PRG2_UART0_TXDGPIO1_24
0x0011C1E4CTRLMMR_PADCONFIG121 AF11UART0_RXDGPIO1_25
0x0011C1E8CTRLMMR_PADCONFIG122 AE11UART0_TXDGPIO1_26
0x0011C1ECCTRLMMR_PADCONFIG123 AG11UART0_CTSnTIMER_IO4SPI0_CS2GPIO1_27
0x0011C1F0CTRLMMR_PADCONFIG124 AD11UART0_RTSnTIMER_IO5SPI0_CS3GPIO1_28
0x0011C1F4CTRLMMR_PADCONFIG125 V24PRG0_PRU0_GPO0PRG0_PRU0_GPI0PRG0_RGMII1_RD0PRG0_PWM3_A0MCASP0_ACLKXGPIO1_29
0x0011C1F8CTRLMMR_PADCONFIG126 W25PRG0_PRU0_GPO1PRG0_PRU0_GPI1PRG0_RGMII1_RD1PRG0_PWM3_B0MCASP0_AFSXGPIO1_30
0x0011C1FCCTRLMMR_PADCONFIG127 W24PRG0_PRU0_GPO2PRG0_PRU0_GPI2PRG0_RGMII1_RD2PRG0_PWM2_A0MCASP0_ACLKRGPIO1_31
0x0011C200CTRLMMR_PADCONFIG128 AA27PRG0_PRU0_GPO3PRG0_PRU0_GPI3PRG0_RGMII1_RD3PRG0_PWM3_A2MCASP0_AFSRGPIO1_32
0x0011C204CTRLMMR_PADCONFIG129 Y24PRG0_PRU0_GPO4PRG0_PRU0_GPI4PRG0_RGMII1_RX_CTLPRG0_PWM2_B0MCASP0_AXR0GPIO1_33
0x0011C208CTRLMMR_PADCONFIG130 V28PRG0_PRU0_GPO5PRG0_PRU0_GPI5PRG0_PWM3_B2MCASP0_AXR1GPIO1_34
0x0011C20CCTRLMMR_PADCONFIG131 Y25PRG0_PRU0_GPO6PRG0_PRU0_GPI6PRG0_RGMII1_RXCPRG0_PWM3_A1MCASP0_AXR2GPIO1_35
0x0011C210CTRLMMR_PADCONFIG132 U27PRG0_PRU0_GPO7PRG0_PRU0_GPI7PRG0_IEP0_EDC_LATCH_IN1PRG0_PWM3_B1PRG0_ECAP0_SYNC_INMCASP0_AXR3GPIO1_36
0x0011C214CTRLMMR_PADCONFIG133 V27PRG0_PRU0_GPO8PRG0_PRU0_GPI8PRG0_PWM2_A1MCASP0_AXR4GPIO1_37
0x0011C218CTRLMMR_PADCONFIG134 V26PRG0_PRU0_GPO9PRG0_PRU0_GPI9PRG0_UART0_CTSnPRG0_PWM3_TZ_INSPI3_CS1MCASP0_AXR5PRG0_IEP0_EDIO_DATA_IN_OUT28GPIO1_38
0x0011C21CCTRLMMR_PADCONFIG135 U25PRG0_PRU0_GPO10PRG0_PRU0_GPI10PRG0_UART0_RTSnPRG0_PWM2_B1SPI3_CS2MCASP0_AXR6PRG0_IEP0_EDIO_DATA_IN_OUT29GPIO1_39
0x0011C220CTRLMMR_PADCONFIG136 AB25PRG0_PRU0_GPO11PRG0_PRU0_GPI11PRG0_RGMII1_TX_CTLPRG0_PWM3_TZ_OUTPRG0_PRU0_GPO15MCASP0_AXR7GPIO1_40
0x0011C224CTRLMMR_PADCONFIG137 AD27PRG0_PRU0_GPO12PRG0_PRU0_GPI12PRG0_RGMII1_TD0PRG0_PWM0_A0PRG0_PRU0_GPO11MCASP0_AXR8GPIO1_41
0x0011C228CTRLMMR_PADCONFIG138 AC26PRG0_PRU0_GPO13PRG0_PRU0_GPI13PRG0_RGMII1_TD1PRG0_PWM0_B0PRG0_PRU0_GPO12MCASP0_AXR9GPIO1_42
0x0011C22CCTRLMMR_PADCONFIG139 AD26PRG0_PRU0_GPO14PRG0_PRU0_GPI14PRG0_RGMII1_TD2PRG0_PWM0_A1PRG0_PRU0_GPO13MCASP0_AXR10GPIO1_43
0x0011C230CTRLMMR_PADCONFIG140 AA24PRG0_PRU0_GPO15PRG0_PRU0_GPI15PRG0_RGMII1_TD3PRG0_PWM0_B1PRG0_PRU0_GPO14MCASP0_AXR11GPIO1_44
0x0011C234CTRLMMR_PADCONFIG141 AD28PRG0_PRU0_GPO16PRG0_PRU0_GPI16PRG0_RGMII1_TXCPRG0_PWM0_A2MCASP0_AXR12MCASP1_AHCLKRGPIO1_45
0x0011C238CTRLMMR_PADCONFIG142 U26PRG0_PRU0_GPO17PRG0_PRU0_GPI17PRG0_IEP0_EDC_SYNC_OUT1PRG0_PWM0_B2PRG0_ECAP0_SYNC_OUTMCASP0_AXR13MCASP1_AHCLKXGPIO1_46
0x0011C23CCTRLMMR_PADCONFIG143 V25PRG0_PRU0_GPO18PRG0_PRU0_GPI18PRG0_IEP0_EDC_LATCH_IN0PRG0_PWM0_TZ_INPRG0_ECAP0_IN_APWM_OUTMCASP0_AXR14MCASP2_AHCLKRGPIO1_47
0x0011C240CTRLMMR_PADCONFIG144 U24PRG0_PRU0_GPO19PRG0_PRU0_GPI19PRG0_IEP0_EDC_SYNC_OUT0PRG0_PWM0_TZ_OUTMCASP0_AXR15MCASP2_AHCLKXGPIO1_48
0x0011C244CTRLMMR_PADCONFIG145 AB28PRG0_PRU1_GPO0PRG0_PRU1_GPI0PRG0_RGMII2_RD0MCASP1_ACLKXGPIO1_49
0x0011C248CTRLMMR_PADCONFIG146 AC28PRG0_PRU1_GPO1PRG0_PRU1_GPI1PRG0_RGMII2_RD1MCASP1_AFSXGPIO1_50
0x0011C24CCTRLMMR_PADCONFIG147 AC27PRG0_PRU1_GPO2PRG0_PRU1_GPI2PRG0_RGMII2_RD2PRG0_PWM2_A2MCASP1_ACLKRGPIO1_51
0x0011C250CTRLMMR_PADCONFIG148 AB26PRG0_PRU1_GPO3PRG0_PRU1_GPI3PRG0_RGMII2_RD3EQEP0_AMCASP1_AFSRGPIO1_52
0x0011C254CTRLMMR_PADCONFIG149 AA25PRG0_PRU1_GPO4PRG0_PRU1_GPI4PRG0_RGMII2_RX_CTLPRG0_PWM2_B2EQEP0_BMCASP1_AXR0MCASP0_AHCLKRGPIO1_53
0x0011C258CTRLMMR_PADCONFIG150 U23PRG0_PRU1_GPO5PRG0_PRU1_GPI5EQEP0_SMCASP1_AXR1MCASP0_AHCLKXGPIO1_54
0x0011C25CCTRLMMR_PADCONFIG151 AB27PRG0_PRU1_GPO6PRG0_PRU1_GPI6PRG0_RGMII2_RXCMCASP1_AXR2GPIO1_55
0x0011C260CTRLMMR_PADCONFIG152 W28PRG0_PRU1_GPO7PRG0_PRU1_GPI7PRG0_IEP1_EDC_LATCH_IN1SPI3_CS0MCASP1_AXR3UART2_TXDGPIO1_56
0x0011C264CTRLMMR_PADCONFIG153 W27PRG0_PRU1_GPO8PRG0_PRU1_GPI8PRG0_PWM2_TZ_OUTMCASP1_AXR4GPIO1_57
0x0011C268CTRLMMR_PADCONFIG154 Y28PRG0_PRU1_GPO9PRG0_PRU1_GPI9PRG0_UART0_RXDSPI3_CS3MCASP1_AXR5PRG0_IEP0_EDIO_DATA_IN_OUT30GPIO1_58
0x0011C26CCTRLMMR_PADCONFIG155 AA28PRG0_PRU1_GPO10PRG0_PRU1_GPI10PRG0_UART0_TXDPRG0_PWM2_TZ_INEQEP0_IMCASP1_AXR6PRG0_IEP0_EDIO_DATA_IN_OUT31GPIO1_59
0x0011C270CTRLMMR_PADCONFIG156 AB24PRG0_PRU1_GPO11PRG0_PRU1_GPI11PRG0_RGMII2_TX_CTLPRG0_PRU1_GPO15MCASP1_AXR7GPIO1_60
0x0011C274CTRLMMR_PADCONFIG157 AC25PRG0_PRU1_GPO12PRG0_PRU1_GPI12PRG0_RGMII2_TD0PRG0_PWM1_A0PRG0_PRU1_GPO11MCASP1_AXR8GPIO1_61
0x0011C278CTRLMMR_PADCONFIG158 AD25PRG0_PRU1_GPO13PRG0_PRU1_GPI13PRG0_RGMII2_TD1PRG0_PWM1_B0PRG0_PRU1_GPO12MCASP1_AXR9GPIO1_62
0x0011C27CCTRLMMR_PADCONFIG159 AD24PRG0_PRU1_GPO14PRG0_PRU1_GPI14PRG0_RGMII2_TD2PRG0_PWM1_A1PRG0_PRU1_GPO13MCASP2_AFSRGPIO1_63
0x0011C280CTRLMMR_PADCONFIG160 AE27PRG0_PRU1_GPO15PRG0_PRU1_GPI15PRG0_RGMII2_TD3PRG0_PWM1_B1PRG0_PRU1_GPO14MCASP2_ACLKRGPIO1_64
0x0011C284CTRLMMR_PADCONFIG161 AC24PRG0_PRU1_GPO16PRG0_PRU1_GPI16PRG0_RGMII2_TXCPRG0_PWM1_A2MCASP2_AXR0GPIO1_65
0x0011C288CTRLMMR_PADCONFIG162 Y27PRG0_PRU1_GPO17PRG0_PRU1_GPI17PRG0_IEP1_EDC_SYNC_OUT1PRG0_PWM1_B2SPI3_CLKMCASP2_AXR1UART2_RXDGPIO1_66
0x0011C28CCTRLMMR_PADCONFIG163 Y26PRG0_PRU1_GPO18PRG0_PRU1_GPI18PRG0_IEP1_EDC_LATCH_IN0PRG0_PWM1_TZ_INSPI3_D0MCASP2_AFSXUART2_CTSnGPIO1_67
0x0011C290CTRLMMR_PADCONFIG164 W26PRG0_PRU1_GPO19PRG0_PRU1_GPI19PRG0_IEP1_EDC_SYNC_OUT0PRG0_PWM1_TZ_OUTSPI3_D1MCASP2_ACLKXUART2_RTSnGPIO1_68
0x0011C294CTRLMMR_PADCONFIG165 AE26PRG0_MDIO0_MDIOPRG2_PWM1_A2MCASP2_AXR2GPIO1_69
0x0011C298CTRLMMR_PADCONFIG166 AE28PRG0_MDIO0_MDCPRG2_PWM1_B2MCASP2_AXR3GPIO1_70
0x0011C29CCTRLMMR_PADCONFIG167 F18NMInPRG2_PWM1_TZ_IN
0x0011C2A0CTRLMMR_PADCONFIG168 F17RESETz
0x0011C2A4CTRLMMR_PADCONFIG169 D19RESETSTATz
0x0011C2A8CTRLMMR_PADCONFIG170 C19PORz_OUT
0x0011C2ACCTRLMMR_PADCONFIG171 E20SOC_SAFETY_ERRORn
0x0011C2B0CTRLMMR_PADCONFIG172 C20TDI
0x0011C2B4CTRLMMR_PADCONFIG173 A20TDO
0x0011C2B8CTRLMMR_PADCONFIG174 A21TMS
0x0011C2BCCTRLMMR_PADCONFIG175 AD9USB0_DRVVBUSGPIO1_71
0x0011C2C0CTRLMMR_PADCONFIG176 AC8USB1_DRVVBUSGPIO1_72
0x0011C2C4CTRLMMR_PADCONFIG177 D27MMC1_DAT3GPIO1_73
0x0011C2C8CTRLMMR_PADCONFIG178 D26MMC1_DAT2GPIO1_74
0x0011C2CCCTRLMMR_PADCONFIG179 E27MMC1_DAT1GPIO1_75
0x0011C2D0CTRLMMR_PADCONFIG180 D28MMC1_DAT0GPIO1_76
0x0011C2D4CTRLMMR_PADCONFIG181 C27MMC1_CLKGPIO1_77
0x0011C2D8CTRLMMR_PADCONFIG182 C28MMC1_CMDGPIO1_78
0x0011C2DCCTRLMMR_PADCONFIG183 B24MMC1_SDCDGPIO1_79
0x0011C2E0CTRLMMR_PADCONFIG184 C24MMC1_SDWPGPIO1_80
0x0011C2E8CTRLMMR_PADCONFIG186 D20I2C0_SCL
0x0011C2ECCTRLMMR_PADCONFIG187 C21I2C0_SDA
0x0011C2F0CTRLMMR_PADCONFIG188 B21I2C1_SCLCPTS0_HW1TSPUSH
0x0011C2F4CTRLMMR_PADCONFIG189 E21I2C1_SDACPTS0_HW2TSPUSH
0x0011C2F8CTRLMMR_PADCONFIG190 D21ECAP0_IN_APWM_OUTSYNC0_OUTCPTS0_RFT_CLKGPIO1_86
0x0011C2FCCTRLMMR_PADCONFIG191 A22EXT_REFCLK1SYNC1_OUTGPIO1_87
0x0011C300CTRLMMR_PADCONFIG192 B22TIMER_IO0SYSCLKOUT0GPIO1_88
0x0011C304CTRLMMR_PADCONFIG193 C23TIMER_IO1OBSCLK0GPIO1_89
0x0011C308CTRLMMR_PADCONFIG194 E19PORz
0x4301C000CTRLMMR_WKUP_PADCONFIG0 V1MCU_OSPI0_CLKMCU_HYPERBUS0_CKWKUP_GPIO0_12
0x4301C004CTRLMMR_WKUP_PADCONFIG1 U1MCU_OSPI0_LBCLKOMCU_HYPERBUS0_CKnWKUP_GPIO0_13
0x4301C008CTRLMMR_WKUP_PADCONFIG2 U2MCU_OSPI0_DQSMCU_HYPERBUS0_RWDSWKUP_GPIO0_14
0x4301C00CCTRLMMR_WKUP_PADCONFIG3 U4MCU_OSPI0_D0MCU_HYPERBUS0_DQ0WKUP_GPIO0_15
0x4301C010CTRLMMR_WKUP_PADCONFIG4 U5MCU_OSPI0_D1MCU_HYPERBUS0_DQ1WKUP_GPIO0_16
0x4301C014CTRLMMR_WKUP_PADCONFIG5 T2MCU_OSPI0_D2MCU_HYPERBUS0_DQ2WKUP_GPIO0_17
0x4301C018CTRLMMR_WKUP_PADCONFIG6 T3MCU_OSPI0_D3MCU_HYPERBUS0_DQ3WKUP_GPIO0_18
0x4301C01CCTRLMMR_WKUP_PADCONFIG7 T4MCU_OSPI0_D4MCU_HYPERBUS0_DQ4WKUP_GPIO0_19
0x4301C020CTRLMMR_WKUP_PADCONFIG8 T5MCU_OSPI0_D5MCU_HYPERBUS0_DQ5WKUP_GPIO0_20
0x4301C024CTRLMMR_WKUP_PADCONFIG9 R2MCU_OSPI0_D6MCU_HYPERBUS0_DQ6WKUP_GPIO0_21
0x4301C028CTRLMMR_WKUP_PADCONFIG10 R3MCU_OSPI0_D7MCU_HYPERBUS0_DQ7WKUP_GPIO0_22
0x4301C02CCTRLMMR_WKUP_PADCONFIG11 R4MCU_OSPI0_CSn0MCU_HYPERBUS0_CSn0WKUP_GPIO0_23
0x4301C030CTRLMMR_WKUP_PADCONFIG12 R5MCU_OSPI0_CSn1MCU_HYPERBUS0_RESETnWKUP_GPIO0_24
0x4301C034CTRLMMR_WKUP_PADCONFIG13 T1MCU_OSPI1_CLKWKUP_GPIO0_25
0x4301C038CTRLMMR_WKUP_PADCONFIG14 R1MCU_OSPI1_LBCLKOMCU_OSPI0_CSn2MCU_HYPERBUS0_RESETOnWKUP_GPIO0_26
0x4301C03CCTRLMMR_WKUP_PADCONFIG15 P2MCU_OSPI1_DQSMCU_OSPI0_CSn3MCU_HYPERBUS0_INTnWKUP_GPIO0_27
0x4301C040CTRLMMR_WKUP_PADCONFIG16 P3MCU_OSPI1_D0WKUP_GPIO0_28
0x4301C044CTRLMMR_WKUP_PADCONFIG17 P4MCU_OSPI1_D1MCU_UART0_RXDMCU_SPI1_CS1WKUP_GPIO0_29
0x4301C048CTRLMMR_WKUP_PADCONFIG18 P5MCU_OSPI1_D2MCU_UART0_TXDMCU_SPI1_CS2WKUP_GPIO0_30
0x4301C04CCTRLMMR_WKUP_PADCONFIG19 P1MCU_OSPI1_D3MCU_UART0_CTSnMCU_SPI0_CS1WKUP_GPIO0_31
0x4301C050CTRLMMR_WKUP_PADCONFIG20 N2MCU_OSPI1_CSn0WKUP_GPIO0_32
0x4301C054CTRLMMR_WKUP_PADCONFIG21 N3MCU_OSPI1_CSn1MCU_HYPERBUS0_WPnMCU_TIMER_IO0MCU_HYPERBUS0_CSn1MCU_UART0_RTSnMCU_SPI0_CS2WKUP_GPIO0_33
0x4301C058CTRLMMR_WKUP_PADCONFIG22 N4MCU_RGMII1_TX_CTLMCU_RMII1_CRS_DVWKUP_GPIO0_34
0x4301C05CCTRLMMR_WKUP_PADCONFIG23 N5MCU_RGMII1_RX_CTLMCU_RMII1_RX_ERWKUP_GPIO0_35
0x4301C060CTRLMMR_WKUP_PADCONFIG24 M2MCU_RGMII1_TD3WKUP_GPIO0_36
0x4301C064CTRLMMR_WKUP_PADCONFIG25 M3MCU_RGMII1_TD2WKUP_GPIO0_37
0x4301C068CTRLMMR_WKUP_PADCONFIG26 M4MCU_RGMII1_TD1MCU_RMII1_TXD1WKUP_GPIO0_38
0x4301C06CCTRLMMR_WKUP_PADCONFIG27 M5MCU_RGMII1_TD0MCU_RMII1_TXD0WKUP_GPIO0_39
0x4301C070CTRLMMR_WKUP_PADCONFIG28 N1MCU_RGMII1_TXCMCU_RMII1_TX_ENWKUP_GPIO0_40
0x4301C074CTRLMMR_WKUP_PADCONFIG29 M1MCU_RGMII1_RXCMCU_RMII1_REF_CLKWKUP_GPIO0_41
0x4301C078CTRLMMR_WKUP_PADCONFIG30 L2MCU_RGMII1_RD3WKUP_GPIO0_42
0x4301C07CCTRLMMR_WKUP_PADCONFIG31 L5MCU_RGMII1_RD2WKUP_GPIO0_43
0x4301C080CTRLMMR_WKUP_PADCONFIG32 M6MCU_RGMII1_RD1MCU_RMII1_RXD1WKUP_GPIO0_44
0x4301C084CTRLMMR_WKUP_PADCONFIG33 L6MCU_RGMII1_RD0MCU_RMII1_RXD0WKUP_GPIO0_45
0x4301C088CTRLMMR_WKUP_PADCONFIG34 L4MCU_MDIO0_MDIOWKUP_GPIO0_46
0x4301C08CCTRLMMR_WKUP_PADCONFIG35 L1MCU_MDIO0_MDCWKUP_GPIO0_47
0x4301C090CTRLMMR_WKUP_PADCONFIG36 Y1MCU_SPI0_CLKWKUP_GPIO0_48MCU_BOOTMODE06
0x4301C094CTRLMMR_WKUP_PADCONFIG37 Y3MCU_SPI0_D0WKUP_GPIO0_49MCU_BOOTMODE07
0x4301C098CTRLMMR_WKUP_PADCONFIG38 Y2MCU_SPI0_D1WKUP_GPIO0_50MCU_BOOTMODE05
0x4301C09CCTRLMMR_WKUP_PADCONFIG39 Y4MCU_SPI0_CS0WKUP_GPIO0_51
0x4301C0A0CTRLMMR_WKUP_PADCONFIG40 AB1WKUP_UART0_RXDWKUP_GPIO0_52
0x4301C0A4CTRLMMR_WKUP_PADCONFIG41 AB5WKUP_UART0_TXDWKUP_GPIO0_53
0x4301C0A8CTRLMMR_WKUP_PADCONFIG42 W1MCU_MCAN0_TXWKUP_GPIO0_54
0x4301C0ACCTRLMMR_WKUP_PADCONFIG43 W2MCU_MCAN0_RXWKUP_GPIO0_55
0x4301C0B0CTRLMMR_WKUP_PADCONFIG44 AF4WKUP_GPIO0_0MCU_SPI1_CLKWKUP_GPIO0_0MCU_BOOTMODE00
0x4301C0B4CTRLMMR_WKUP_PADCONFIG45 AF3WKUP_GPIO0_1MCU_SPI1_D0WKUP_GPIO0_1MCU_BOOTMODE01
0x4301C0B8CTRLMMR_WKUP_PADCONFIG46 AE3WKUP_GPIO0_2MCU_SPI1_D1WKUP_GPIO0_2MCU_BOOTMODE02
0x4301C0BCCTRLMMR_WKUP_PADCONFIG47 AD1WKUP_GPIO0_3MCU_SPI1_CS0WKUP_GPIO0_3MCU_BOOTMODE03
0x4301C0C0CTRLMMR_WKUP_PADCONFIG48 AC3WKUP_GPIO0_4MCU_MCAN1_TXMCU_SPI0_CS3MCU_ADC_EXT_TRIGGER0WKUP_GPIO0_4MCU_BOOTMODE04
0x4301C0C4CTRLMMR_WKUP_PADCONFIG49 AD3WKUP_GPIO0_5MCU_MCAN1_RXMCU_SPI1_CS3MCU_ADC_EXT_TRIGGER1WKUP_GPIO0_5
0x4301C0C8CTRLMMR_WKUP_PADCONFIG50 AC2WKUP_GPIO0_6WKUP_UART0_CTSnMCU_CPTS0_HW1TSPUSHWKUP_GPIO0_6
0x4301C0CCCTRLMMR_WKUP_PADCONFIG51 AC1WKUP_GPIO0_7WKUP_UART0_RTSnMCU_CPTS0_HW2TSPUSHWKUP_GPIO0_7
0x4301C0D0CTRLMMR_WKUP_PADCONFIG52 AC5WKUP_GPIO0_8MCU_CPTS0_TS_SYNCWKUP_GPIO0_8MCU_BOOTMODE08
0x4301C0D4CTRLMMR_WKUP_PADCONFIG53 AB4WKUP_GPIO0_9MCU_CPTS0_TS_COMPWKUP_GPIO0_9MCU_BOOTMODE09
0x4301C0D8CTRLMMR_WKUP_PADCONFIG54 AB3WKUP_GPIO0_10MCU_EXT_REFCLK0MCU_CPTS0_RFT_CLKMCU_SYSCLKOUT0WKUP_GPIO0_10
0x4301C0DCCTRLMMR_WKUP_PADCONFIG55 AB2WKUP_GPIO0_11MCU_OBSCLK0MCU_TIMER_IO1MCU_CLKOUT0WKUP_GPIO0_11
0x4301C0E0CTRLMMR_WKUP_PADCONFIG56 AC7WKUP_I2C0_SCL
0x4301C0E4CTRLMMR_WKUP_PADCONFIG57 AD6WKUP_I2C0_SDA
0x4301C0E8CTRLMMR_WKUP_PADCONFIG58 AD8MCU_I2C0_SCL
0x4301C0ECCTRLMMR_WKUP_PADCONFIG59 AD7MCU_I2C0_SDA
0x4301C0F0CTRLMMR_WKUP_PADCONFIG60 AA5PMIC_POWER_EN1
0x4301C0F4CTRLMMR_WKUP_PADCONFIG61 W3MCU_SAFETY_ERRORn
0x4301C0F8CTRLMMR_WKUP_PADCONFIG62 W4MCU_RESETz
0x4301C0FCCTRLMMR_WKUP_PADCONFIG63 V3MCU_RESETSTATz
0x4301C100CTRLMMR_WKUP_PADCONFIG64 V2MCU_PORz_OUT
0x4301C104CTRLMMR_WKUP_PADCONFIG65 AA4TCK
0x4301C108CTRLMMR_WKUP_PADCONFIG66 AA3TRSTn
0x4301C10CCTRLMMR_WKUP_PADCONFIG67 AA2EMU0
0x4301C110CTRLMMR_WKUP_PADCONFIG68 AA1EMU1
0x4301C114CTRLMMR_WKUP_PADCONFIG69 Y5PMIC_POWER_EN0
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