ZHCSLA7C December 2019 – September 2023 AM6526 , AM6528 , AM6546 , AM6548
PRODUCTION DATA
NO. | PARAMETER | DESCRIPTION(1) | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|---|
OLDI1 | tt(LHTT) | Low-to-high transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0 (Fast rise/fall disabled) | 0.5 | ns | ||
Low-to-high transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1 (Fast rise/fall enabled) | 0.25 | ns | ||||
OLDI2 | tt(HLTT) | High-to-low transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 0 (Fast rise/fall disabled) | 0.5 | ns | ||
High-to-low transition time of LVDS differential signals: OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0], with BOOSTA_EN = 1 (Fast rise/fall enabled) | 0.25 | ns | ||||
OLDI3 | tc(CLK) | Output pixel clock period (OLDI0_CLKP/N) | 6.06 | 110.01 | ns | |
OLDI4 | tw(BIT) | Output bit width (OLDI0_AxP/N, x = [3:0]) | 1 | UI(2) | ||
OLDI5 | t(TPPx, x=[6:0]) | Output pulse positions normalized for each bit (OLDI0_AxP/N, x = [3:0]) | 7-1 | UI(2) | ||
OLDI6 | Δt(TPP) | Variation of pulse positions for each bit from their normalized center (OLDI0_AxP/N, x = [3:0]) | 0.1 | UI(2) | ||
OLDI7 | tsk(TCCS) | Output channel to channel skew (OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0]) | 50 | ps | ||
OLDI8 | tj(TJCC) | Output jitter cycle-to-cycle (OLDI0_CLKP/N, OLDI0_AxP/N, x = [3:0]) | 0.04 | UI(2) | ||
OLDI9 | tj(IJIT) | Total jitter tolerance (Includes data to clock skew, pulse position variation from normalized edges (OLDI0_AxP/N, x = [3:0]) | 0.25 | UI(2) |
For more information, see section Display Subsystem (DSS) in the device TRM.